Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1999-07-30
2000-09-05
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714738, G01R 3128
Patent
active
061158356
ABSTRACT:
The present invention is directed to a system comprised of a computer, at least one integrated circuit tester, a communications link enabling communications between the integrated circuit tester and the computer, and a computer-readable medium. The computer-readable medium contains a sequence of instructions that, when executed, create a set of tests for integrated circuit testing. The set of tests may include only those tests that are calculated to be statistically significant. A second set of tests may be created that includes only those tests that are calculated to be statistically insignificant. The computer monitors the test results and moves tests between the two sets to ensure that only statistically significant tests are in the first group and that only statistically insignificant tests are in the second group.
REFERENCES:
patent: 4176780 (1979-12-01), Sacher et al.
patent: 5381417 (1995-01-01), Loopik et al.
patent: 5745501 (1998-04-01), Garner et al.
patent: 5771243 (1998-06-01), Lee et al.
patent: 5935264 (1999-08-01), Nevill et al.
Barnett Gregory A.
Ford, Jr. Bruce J.
Nevill Leland R.
Nguyen Than Huu
Micro)n Technology, Inc.
Tu Trinh L.
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