Method and apparatus for detecting array degradation and...

Details Method and apparatus for detecting array degradation and... Method and apparatus for detecting array degradation and...

2007-05-29

2007-05-29

Kerveros, James C (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10815248

ABSTRACT:
A method and apparatus are provided for detecting degradation, such as, array degradation and logic degradation, in integrated circuits (ICs) including application specific integrated circuits (ASICs). A monitor built-in self-test (MBIST) engine coupled to at least one monitor element that is defined by predefined circuit elements in the integrated circuit. The MBIST engine is used for controlling operation of at least one monitor element for communicating with monitor bits to identify degradation of signal, timing and voltage margins.

REFERENCES:
patent: 5652729 (1997-07-01), Iwata et al.
patent: 6295237 (2001-09-01), Pochmuller
patent: 6483764 (2002-11-01), Hsu et al.
patent: 6640321 (2003-10-01), Huang et al.

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