Method and apparatus for detecting and reporting failed processo

Details Method and apparatus for detecting and reporting failed processo Method and apparatus for detecting and reporting failed processo

1997-09-18

2000-01-11

Hua, Ly V.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714736, G06F 1500, G06F 1100

Patent

active

06014758&

ABSTRACT:
A reset signal is asserted to a processor. In response to the reset signal, the processor normally performs an instruction fetch cycle to a predetermined address. If the processor fails to perform the instruction fetch cycle or fails to perform the fetch cycle to the predetermined address within a predetermined period of time, an indication is provided that the processor reset has failed.

REFERENCES:
patent: 4303986 (1981-12-01), Lans
patent: 4594685 (1986-06-01), Owens
patent: 4763296 (1988-08-01), Gercekci
patent: 4809280 (1989-02-01), Shonaka
patent: 5249188 (1993-09-01), McDonald
patent: 5513319 (1996-04-01), Finch et al.
patent: 5530946 (1996-06-01), Bouvier et al.
patent: 5535405 (1996-07-01), Byers et al.

Affiliated with

Also associated with

Rating

Method and apparatus for detecting and reporting failed processo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for detecting and reporting failed processo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for detecting and reporting failed processo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1470831