Patent
1985-10-04
1988-01-26
Edlow, Martin H.
357 6875, H01L 2314, H01L 2354, H01L 2701
Patent
active
047219955
ABSTRACT:
An integrated circuit semiconductor device of very large scale (VLSI) formed in a wafer, namely a wafer IC, is disclosed. In a wafer, a number of circuit blocks are formed in a matrix, being isolated from each other by an intermediate area locating between the circuit blocks. These circuit blocks are connected to interconnecting circuits which are formed on an insulative film in order to complete the wafer IC. The connection is performed by bonding corresponding bonding means, such as pads, disposed on the circuit blocks, repair chips and the interconnecting circuits by a conventional bonding process. With this structure of the wafer IC, the circuit blocks can be accessed easily by a computer aided testing apparatus in advance and the defective circuit blocks can be replaced by good ones, namely repair chips prepared in advance, without any rework of the interconnecting circuits. Bonding pads disposed on the circuit blocks and repair chips are arranged in a predetermined layout pattern for interchangeable bonding, by which the replacement of bad circuit blocks become possible regardless the location of the defective circuit blocks. Two types of the interconnecting film are disclosed for overcoming top surfaces of the repair chips, protruding from the surface of the wafer.
REFERENCES:
patent: 4021838 (1977-05-01), Warwick
patent: 4136356 (1979-01-01), Kusano
patent: 4246595 (1981-01-01), Noyori et al.
Clark S. V.
Edlow Martin H.
Fujitsu Limited
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