Method and apparatus for detecting and correcting anomalies in f

Details Method and apparatus for detecting and correcting anomalies in f Method and apparatus for detecting and correcting anomalies in f

1998-07-20

2000-08-08

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714752, 714 48, 714758, G06F 1100

Patent

active

061016241

ABSTRACT:
A method and means for detecting and correcting anomalies in a RAM-based FPGA by comparing CRC residues over portions of the RAM-stored connection bitmap with prestored residues derived from uncorrupted copies of the same bitmap portions. A mismatch selectively invokes either error reporting to the chip only, error reporting and immediate verification testing of counterpart FPGA chip functions, or error reporting, parity-based correction of the words in error, reprogramming of the chip functions with the corrected words, and verification testing.

REFERENCES:
patent: 3976982 (1976-08-01), Eiselen
patent: 4092732 (1978-05-01), Ouchi
patent: 4761785 (1988-08-01), Clark et al.
patent: 5744979 (1998-04-01), Goetting
patent: 5959987 (1999-09-01), Humphrey et al.
patent: 5991270 (1999-11-01), Zwan et al.

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