Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-24
2011-05-24
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S727000, C714S729000, C716S100000, C716S101000, C716S110000, C716S138000
Reexamination Certificate
active
07949915
ABSTRACT:
The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.
REFERENCES:
patent: 4872169 (1989-10-01), Whetsel
patent: 6088822 (2000-07-01), Warren
patent: 6430718 (2002-08-01), Nayak
patent: 6456961 (2002-09-01), Patil et al.
patent: 6587981 (2003-07-01), Muradali et al.
patent: 6631504 (2003-10-01), Dervisoglu et al.
patent: 6665828 (2003-12-01), Arimilli et al.
patent: 6708144 (2004-03-01), Merryman et al.
patent: 7006960 (2006-02-01), Schaumont et al.
patent: 7181705 (2007-02-01), Dervisoglu et al.
patent: 7188330 (2007-03-01), Goyal
patent: 7296200 (2007-11-01), Park et al.
patent: 2003/0046015 (2003-03-01), Gotoh et al.
patent: 2003/0131296 (2003-07-01), Park et al.
patent: 2003/0131327 (2003-07-01), Dervisoglu et al.
patent: 2003/0145286 (2003-07-01), Pajak et al.
patent: 2004/0002832 (2004-01-01), Chan
patent: 2005/0097416 (2005-05-01), Plunkett
patent: 2005/0262460 (2005-11-01), Goyal et al.
patent: 2005/0262465 (2005-11-01), Goyal
patent: 2006/0179373 (2006-08-01), Ishikawa
patent: 2006/0282729 (2006-12-01), Dastidar
patent: 2007/0094629 (2007-04-01), Alter et al.
patent: 2008/0141087 (2008-06-01), Whetsel
patent: 2009/0144592 (2009-06-01), Chakraborty et al.
patent: 2009/0144594 (2009-06-01), Chakraborty et al.
patent: 2009/0193304 (2009-07-01), Chakraborty et al.
patent: 2009/0193306 (2009-07-01), Chakraborty et al.
patent: 62 093672 (1987-04-01), None
patent: WO 2007/049171 (2007-05-01), None
patent: WO 2007/049171 (2007-05-01), None
patent: WO 2005/078465 (2008-08-01), None
International Search Report and Written Opinion, dated Feb. 19, 2009, in PCT/US2008/013109, Alcatel-Lucent USA Inc., Applicant, 15 pages.
Melocco K et al: “A comprehensive approach to assessing and analyzing 1149.1 test logic” Proceedings International Test Conference 2003. (ITC). Charlotte, NC, Sep. 30-Oct. 2, 2003; [International Test Conference], New York, NY : IEEE, US, vol. 2, Sep. 30, 2003, pp. 40-49, XP010685379 ISBN: 978-0-7803-8106-3.
Brian Foutz et al: “Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC methodology” Test Symposium, 2006. ATS '06. 15thAsian, IEEE, PI, Nov. 1, 2006, pp. 381-388, XP031030539 ISBN: 978-0-695-2628-7.
International Search Report and Written Opinion dated Mar. 19, 2009 in International Application No. PCT/US2008/013110, Alcatel-Lucent USA Inc., Applicant, 15 pages.
International Search Report and Written Opinion dated Mar. 19, 2009 in International Application No. PCT/US2008/013054than, Alcatel-Lucent USA Inc., Applicant, 15 pages.
“IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE Std. 1149.1-2001.
IEEE 1687 IJTAG HW Proposal, 1687 Proposed Hardware Architecture Summary Update, v7.0, Jun. 25, 2007.
“Hierarchical Scan Description Language Syntax Specification,” ASSET InterTech, Inc. 1997.
IEEE Standard VHDL Language Reference Manual, IEEE Std 1076, 2000 Edition.
Rearick, J., et al., “IJTAG (Internal JTAG): A Step Toward a DFT Standard,” 2005, IEEE pp. 1-10.
Carlsson, G., et al., “Protocol Requirements in an SJTAG/IJTAG Environment,” 2007, IEEE, pp. 1-9.
Crouch, A., et al., “IJTAG: The Path to Organized Instrument Connectivity,” 2007, IEEE, pp. 1-10.
Eklow, B., et al., “Microsoft Power Point—ETS06—IJTAG-Embedded-Tutorial-v2,” May 23, 2006, IEEE P1687 (IJTAG), pp. 1-42.
PCT Search Report and The Written Opinion of the International Searching Authority, or the Declaration, dated May 11, 2009, in PCT/US2009/000453, Alcatel-Lucent USA Inc., Applicant, 15 pages.
PCT Search Report and the Written Opinion of the International Searching Authority, or the Declaration, dated May 11, 2009, in PCT/US2009/000346, Alcatel-Lucent USA Inc., Applicant, 15 pages.
Chakraborty Tapan J.
Chiang Chen-Huan
Goyal Suresh
Portolan Michele
Van Treuren Bradford Gene
Alcatel-Lucent USA Inc.
Trimmings John P
Wall & Tong LLP
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