Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-11-22
2008-11-18
Chaudry, Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S800000
Reexamination Certificate
active
07454685
ABSTRACT:
A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.
REFERENCES:
patent: 6307487 (2001-10-01), Luby
patent: 6567465 (2003-05-01), Goldstein et al.
patent: 6614366 (2003-09-01), Luby
patent: 6757122 (2004-06-01), Kuznetsov et al.
patent: 6789227 (2004-09-01), De Souza et al.
patent: 7318186 (2008-01-01), Yokokawa et al.
patent: 7395494 (2008-07-01), Lee et al.
patent: 2005/0138519 (2005-06-01), Boutillon et al.
patent: 2005/0149840 (2005-07-01), Lee et al.
patent: 2005/0283707 (2005-12-01), Sharon et al.
patent: 1405981 (2003-03-01), None
patent: 1713530 (2005-12-01), None
patent: 1 610 466 (2005-12-01), None
Eran Sharon et al., “An Efficient Message-Passing Schedule for LDPC Decoding”, Proc., IEEE Convention of Electrical and Electronics Engineers in Israel, Sep. 6, 2004, pp. 223-226, XP010743004.
Guilloud Frederic, “Architecture Générique de Décodeur de Codes LDPC”, Thèse De Docteur De L'ecole Nationale De Supérieure Des Télécommunications, Jul. 2, 2004, pp. 1-166, XP002370625.
Rich Echard et al., “The Pi-Rotation Low-Density Parity Check Codes”, Proc., IEEE Global Telecommunications Conf., GLOBECOM '01, San Antonio, TX, Nov. 25, 2001, pp. 980-984, vol. 2 of 6, XP001099251.
Kim Han-Ju
Kim Min-Goo
Kim Sang-Hyo
Park Sung-Jin
Chaudry Mujtaba K
Roylance Abrams Berdo & Goodman LLP
Samsung Electronics Co,. Ltd.
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