Method and apparatus for debugging a multicore system

Details Method and apparatus for debugging a multicore system Method and apparatus for debugging a multicore system

2006-02-22

2009-08-25

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S012000, C710S001000, C703S020000

Reexamination Certificate

active

07581087

ABSTRACT:
Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating the stop. The other processing core receives the first hardware signal and stops operation. Both processing cores stop at approximately the same time based on the first hardware signal. Thereafter, the first or second processing core receives another software command to resume operation and generates a second hardware signal indicating resumption of operation. The other processing core receives the second hardware signal and resumes operation. Both processing cores resume at approximately the same time based on the second hardware signal. The first and second hardware signals may come from the same or different processing cores.

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