Method and apparatus for creating a gate optimization...

Details Method and apparatus for creating a gate optimization... Method and apparatus for creating a gate optimization...

2011-03-01

2011-03-01

Deo, Duy-Vu N (Department: 1713)

Data processing: measuring, calibrating, or testing

Calibration or correction system

C356S072000, C356S311000

Reexamination Certificate

active

07899637

ABSTRACT:
The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.

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K. Bernstein, et al; High-Performance CMOS Variability in the 65-nm Regime and Beyond; IBM Journal of R&D; Aug. 2006.
U.S. Appl. No. 11/762,258, Yamashita et al; “Method and Apparatus for Optimizing a Gate Channel”.

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