Abrading – Precision device or process - or with condition responsive... – With indicating
Reexamination Certificate
1999-08-11
2001-08-21
Morgan, Eileen P. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
With indicating
C451S011000, C451S041000, C451S054000, C451S063000, C451S285000, C451S287000
Reexamination Certificate
active
06276989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the planarization of semiconductor wafers, and more particularly, to a method and apparatus for controlling within-wafer uniformity in chemical mechanical polishing.
2. Description of the Related Art
Chemical mechanical polishing (CMP) is a widely used means of planarizing silicon dioxide as well as other types of layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, the surface of the wafer is mechanically and chemically polished.
As semiconductor devices are scaled down, the importance of chemical mechanical polishing to the fabrication process increases. In particular, it becomes increasingly important to control and minimize within-wafer topography variations. For example, in one embodiment, to minimize spatial variations in downstream photolithography and etch processes, it is necessary for the oxide thickness of a wafer to be as uniform as possible (i. e., it is desirable for the surface of the wafer to be as planar as possible.)
Those skilled in the art will appreciate that a variety of factors may contribute to producing variations across the post-polish surface of a wafer. For example, variations in the surface of the wafer may be attributed to drift of the chemical mechanical polishing device. Typically, a chemical mechanical polishing device is optimized for a particular process, but because of chemical and mechanical changes to the polishing pad during polishing, degradation of process consumables, and other processing factors, the chemical mechanical polishing process may drift from its optimized state.
Generally, within-wafer uniformity variations (i.e., surface non-uniformity) are produced by slight differences in polish rate at various positions on the wafer.
FIG. 1
illustrates two radial profiles of surface non-uniformity typically seen after an oxide polish of a wafer. The dished topography is often referred to as a center-fast polishing state because the center of the wafer polishes at a faster rate than the edge of the wafer. The domed topography is designated center-slow because the center of the wafer polishes at a slower rate than the edge of the wafer. For obvious reasons, the dished topography may also be referred to as edge-slow, and the domed topography may also be referred to as edge-fast.
In addition to process drift, pre-polish surface non-uniformity of the wafer may also contribute to producing variations across the post-polish surface of the wafer. For example, prior to being polished, the radial profile of the wafer may be non-uniform (e.g., the surface may exhibit characteristics that are center-fast, center-slow, etc.), and the post-polish surface non-uniformity of the wafer may be exacerbated by the pre-polish condition of the wafer.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method of controlling surface non-uniformity of a process layer is provided. The method includes receiving a first lot of wafers, and polishing a process layer of the first lot of wafers. A control variable of the polishing operations is measured after the polishing is performed on the process layer. A first adjustment input for an arm oscillation length of a polishing tool is determined based on the measurement of the control variable. A process layer of a second lot of wafers is polished using the adjustment input for the arm oscillation length.
In another aspect of the present invention, a controller for controlling surface non-uniformity of a process layer is provided The controller includes an optimizer and an interface. The optimizer is adapted to determine a first adjustment input for arm oscillation length of a polishing tool based on a measurement of a control variable from a first lot of wafers. The interface is adapted to provide the first adjustment input to the polishing tool for polishing a second lot of wafers.
REFERENCES:
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patent: 6093651 (2000-07-01), Andideh et al.
patent: 6120348 (2000-09-01), Fujita et al.
patent: 6146241 (2000-11-01), Lee et al.
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Boning et al., “Practical issues in run by run process control,” Proceeding of Advanced Semiconductor Manufacturing Conference, 1995.
Campbell W. Jarrett
Lansford Jeremy
Raeder Christopher H.
Advanced Micro Devices , Inc.
Morgan Eileen P.
Williams Morgan & Amerson P.C.
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