Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Patent
1998-06-23
2000-07-25
Butler, Dennis M.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
713501, 713600, G06F 106
Patent
active
060947276
ABSTRACT:
A data rate control circuit that is programmable between a first data rate and a second data rate. The data rate control circuit is formed by a clocking circuit and a switching circuit. The clocking circuit receives a first clock signal on a first input line and has a second input line which receives either the second clock signal or a steady state voltage. The switching circuit selectively couples the second clock signal or the steady state voltage to the clocking circuit. When the clocking circuit receives the second clock signal, the clocking circuit clocks at a double data rate, and when the clocking circuit receives the steady state voltage, the clocking circuit clocks at a single data rate. The switching circuit includes a switch that switches the output signal between the second clock signal and the steady state voltage. The clocking circuit can be any of many circuits known to those skilled in the art including a shift register or counter latch.
REFERENCES:
patent: 4527075 (1985-07-01), Zbinden
patent: 5128560 (1992-07-01), Chern et al.
patent: 5128563 (1992-07-01), Hush et al.
patent: 5165046 (1992-11-01), Hesson
patent: 5274276 (1993-12-01), Casper et al.
patent: 5329186 (1994-07-01), Hush et al.
patent: 5347179 (1994-09-01), Casper et al.
patent: 5349247 (1994-09-01), Hush et al.
patent: 5410683 (1995-04-01), Al-Khairi
patent: 5564042 (1996-10-01), Ventrone et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5627487 (1997-05-01), Keeth
patent: 5758134 (1998-05-01), Imel et al.
patent: 5867453 (1999-02-01), Wang et al.
patent: 5874845 (1999-02-01), Hynes
patent: 5877636 (1999-03-01), Truong et al.
patent: 6016548 (2000-01-01), Nakamura et al.
Descriptive literature entitled, "400MHz SL.DRAM, 4M.times.16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," SLDRAM Consortium Advance Sheet, published throughout the United States, pp. 1-22.
"Draft Standard for a High-Speed Memory Interface (SyncLink)," Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc. New York, NY, pp. 1-56.
Maneatis, J., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques", IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Butler Dennis M.
Micro)n Technology, Inc.
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