Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-12
2011-10-25
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S727000
Reexamination Certificate
active
08046648
ABSTRACT:
A method and apparatus allows controlling a plurality of test operations in an electronic device, and in particular a volatile or non-volatile memory device in which a test mode has already been established, without the need for additional device connections. One such operation may be switching device operation from test mode to functional mode, the normal operating mode of the device. Other test operations include support of continuity testing by external circuitry, support of externally accessing device identification with which the device has been previously programmed, support of built in self-test, support of self-repair and support of other operations determined as needs arise.
REFERENCES:
patent: 4566104 (1986-01-01), Bradshaw et al.
patent: 5155704 (1992-10-01), Walther et al.
patent: 6256761 (2001-07-01), Deix et al.
patent: 7372760 (2008-05-01), Nagatomi et al.
patent: 2003/0212939 (2003-11-01), Baker
IEEE Std 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture.
Gaffin Jeffrey A
Nguyen Steve
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