Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-28
2003-06-03
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000, C438S913000, C118S429000
Reexamination Certificate
active
06573183
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the fabrication step of electroplating in the manufacture of semiconductor wafers and/or integrated circuit devices (IC devices). In addition, the invention relates to the methods of minimizing particulate contamination occurring during the electroplating process commonly used as a fabrication step of semiconductor wafers and/or IC devices.
Electroplating is widely used for metal deposition in the manufacture of printed circuit boards, and more recently has become popular in the manufacture of IC devices. A variety of conductor materials are used in the interconnect structure of IC devices including aluminum, aluminum alloys, polysilicon with an overlaid metal silicide layer, and tungsten. More recently, copper has been used in IC device fabrication as an interconnect material. A popular method of depositing copper during IC device fabrication is electroplating.
Interconnect structures are those structures on an IC device that connect different levels of a multi-level-interconnect IC device, and include contact holes and/or vias. Contact holes are holes in a PMD (pre-metal dielectric), which is a dielectric layer between a polysilicon gate and a metal layer. Contact holes allow electrical connections between a metal layer and the polysilicon and/or the silicon) wafer substrate. Vias allow the contact between different metal layers on the IC device.
These interconnect materials are deposited on the wafer using different techniques including sputtering, chemical vapor deposition and electroplating. In the case of electroplating copper, a wafer or chip first requires an adhesion/barrier layer and a seed layer. The materials used to form the adhesion/barrier layer, and the methods for application of the adhesion/barrier layer, are known to those skilled in art.
The copper electroplating process of semiconductor wafers and/or IC devices involves the exposure of a wafer; face down, in an electrolyte bath so that the top patterned surface of the wafer is in contact with, or immersed in the electrolyte bath. The electroplating process is performed in an electroplating tool, which is shown in FIG.
1
. As shown in
FIG. 1
, the electroplating tool
11
generally includes an electroplating plating chamber
12
in which a semiconductor wafer
13
is disposed “face-down”. Sealing mechanisms, known to those skilled in the art, seal a backside of the wafer
13
from the electroplating process. An electroplating bath (or solution)
15
is supplied to the chamber
12
through a conduit
14
. The conduit
14
directs the solution (or bath) to the chamber, so that the wafer is adequately exposed to the electrolytic solution for deposition of copper on the wafer surface.
A commonly used electroplating bath is an electrolyte solution containing copper sulfate, sulfuric acid and water. Moreover, the electrolyte solution includes additives to control the plating process. The additives are organic and inorganic compounds commonly used in the electroplating process that control the rate of copper plating and plating behavior on the wafer surface. The additives are commonly referred to as levelers, brighteners or accelerators.
In an electroplating chamber, the wafer
13
acts as a cathode for copper deposition. The tool
11
is also equipped with a solid copper anode, which replaces copper ions removed as a result of electroplating. The entire electroplating process for a semiconductor wafer may take one to three minutes.
After electroplating, the wafers are then chemically rinsed and dried. In addition, the wafers are annealed to stabilize the copper microstructure formed on the wafer surface. After the annealing step, the wafers are subjected to a chemical-mechanical planarization (CMP) step in which the copper metal deposited on the wafer, outside a via, trench or contact hole, is polished back to leave the features (holes, vias or trenches) filled with copper. The CMP processes available in the production of semiconductor wafers are well known in the art. The CMP process not only removes any excess copper, but also achieves the required planarization across the wafer surface.
Contamination of the wafer may occur in two forms in the electroplating process: particulate contamination and “pits” caused by air/gas bubbles. Since the composition of the electroplating bath is acidic, particles in the bath have a tendency to deposit on the wafer surface during the electroplating process. The presence of particles on the wafer surface leads to enhanced or suppressed copper plating, resulting in the formation of a non-homogenous, defect-ridden copper film across the wafer surface. In addition, as the wafer is placed in the plating cell face down, air bubbles are trapped during the electroplating process against the wafer surface. These air bubbles can lead to “microvoids” or “pits” on the wafer surface. These microvoids or pits compromise the copper film reliability and can lead to device failure.
Present methods used to prevent such contamination include minimizing handling and exposure of wafers in clean rooms, or reducing particulate contamination in a previous step of copper seed deposition. In addition, wafers may be introduced into the electroplating chamber at an angle. However, these methods have proven ineffective. Particulate contamination invariably occurs and cannot by completely eliminated. In addition, the angled introduction of the wafer can lead to a copper thickness gradient across the wafer.
SUMMARY OF THE INVENTION
In order to minimize contamination or prevent defects on semiconductor wafer surfaces or IC devices, an electroplating process is adapted to perform vibrational scrubbing during the electroplating process. An electroplating tool is equipped with a transducer for generating energy waves within an electroplating solution. A top surface of the semiconductor wafer is exposed to the electroplating solution containing those components known in the art such as Cu
2
SO
4
, H
2
SO
4
, water and various organic and inorganic additives to control variables of the electroplating process. During the electroplating process the transducer intermittently generates sonic energy waves at selected frequencies and wavelengths, for a timed duration. The sonic waves agitate and remove particulate contamination and trapped air bubbles. The transducer preferably generates the sonic energy waves for pulses up to 1 to 2 seconds in length. Once the electroplating process is complete, the semiconductor wafers are removed free of contaminants and potential defects that may normally occur in the electroplating process.
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patent: 1 061 159 (2000-12-01), None
patent: 6-256998 (1994-09-01), None
patent: 2000-3886 (2000-01-01), None
H. Sonoda and T. Kamiya, “Stirring Method of Plating Liquid,” JP 6-256998 A, Sep. 1994 (English Translation).*
S. Wolf and R.N. Tauber,Silicon Processing for VLSI Era, vol. 1—Process Technology, pp. 134-137, Second Edition (2000), Published by Lattice Press, Sunset Beach, California.
Merchant Sailesh Mansinh
Oh Minseok
Ramappa Deepak A.
Agere Systems Inc.
Jr. Carl Whitehead
Smoot Stephen W.
Wolter, Esq. Robert L.
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