Method and apparatus for controlling a voltage level

Details Method and apparatus for controlling a voltage level Method and apparatus for controlling a voltage level

2007-08-28

2007-08-28

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S112000, C326S119000

Reexamination Certificate

active

11102881

ABSTRACT:
A voltage level control device operable to control a voltage level supplied from a first voltage level source to circuitry, said circuitry being arranged between said first voltage level source and a second voltage level source, said first and second voltage level sources being operable to output different voltage levels; said voltage level control device comprising: a power transistor operable to be connected between said first voltage level source and said circuitry, said power transistor comprising a sleep signal input operable to receive a sleep signal; a switching device arranged in parallel with said power transistor and comprising a sleep signal input operable to receive a pseudo sleep signal; wherein said voltage level control device is operable in dependence upon said sleep signal and said pseudo sleep signal to output to said circuitry an output voltage said output voltage comprising one of three voltage levels, said three voltage levels lying between voltage levels output by said first and second voltage sources.

REFERENCES:
patent: 5332929 (1994-07-01), Chiang
patent: 5959927 (1999-09-01), Yamagata et al.
patent: 6049245 (2000-04-01), Son et al.
patent: 2002/0000873 (2002-01-01), Tanizaki et al.
patent: 2003/0102904 (2003-06-01), Mizuon et al.
patent: 2006/0091913 (2006-05-01), Bhattacharya

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