Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-02-26
2004-03-16
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S016000
Reexamination Certificate
active
06708303
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to a scan circuit and, more particularly, to a method and apparatus for controlling a separate scan output of a scan circuit.
BACKGROUND OF THE INVENTION
When designing digital electronic circuits, an important consideration in many applications is to include provisions for testing and/or debugging the resulting circuit. This is particularly important when the circuit will be fabricated as an integrated circuit, because discrete points or nodes within the circuit are not readily accessible for purposes of test or debug.
One well-established approach is the Williams and Angell technique, and is also known as a serial scan technique. Under the Williams and Angell technique, all storage elements in a circuit, except random access memory (RAM) and read-only memory (ROM), are implemented using scan flip-flops, which each have two data inputs. In particular, each such flip-flop has a normal data input and a scan data input, and also has a mode control input to select between the normal data input and the scan data input. Each flip-flop also has a single clock input, which is used for both modes.
A typical scan flip-flop may be implemented with a D-type flip-flop and a two-to-one multiplexer, the multiplexer having two data inputs which respectively serve as the normal and scan data inputs, having a select input which serves as the mode control input, and having a data output which is coupled to the data input of the D-type flip-flop.
The Williams and Angell technique further provides that all scan flip-flops in the circuit are interconnected so as to form one long serial shift register, in particular by coupling the data or “Q” output of each flip-flop to the scan data input of another flip-flop. The scan data input of the first flip-flop in the chain can receive serial test patterns from a tester, and the data output of the last flip-flop in the chain can be coupled to the tester so that the tester can receive data output from the chain. The chain connections are used only when the circuit is operating in a scan mode, and not when the circuit is operating in a normal mode.
In such a circuit, the scan mode can be used to facilitate testing or debugging in two distinct ways. First, with the circuit in the scan mode, a data pattern can be introduced serially into the chain of flip-flops, so that each flip-flop in the chain is set to a respective predetermined logic state. The circuit can then be switched to the normal mode, so that operation in the normal mode then proceeds from a known initial state of the circuit.
Second, use of the scan mode may be appropriate after the circuit has been operating for a period of time in the normal mode. The circuit can be switched from the normal mode to the scan mode, and then the data present in all of the flip-flops in the circuit can be read out serially from the chain of flip-flops. The resulting data is a snapshot of the current operational state of the entire circuit. If the output of the last flip-flop in the chain is connected to the scan input of the first flip-flop in the chain while this data is being serially extracted, the data will be reintroduced into the chain as it is being serially read out. Thus, after the last bit of information is serially read out, the entire chain will be returned to the precise state which it had when the serial readout began. The circuit can then be shifted from the scan mode back to the normal mode in order to continue normal operation from the point at which it was interrupted.
Alternatively, instead of shifting back into the chain the data which is being serially read out, a different data pattern can be shifted into the chain in order to set each of the flip-flops to a known state. The circuit can then be shifted from the scan mode back to the normal mode, so that it continues normal operation from the known state, rather from the state that it was in when the normal mode was interrupted.
When a circuit using the Williams and Angell technique is implemented, a software program is often used to lay out the locations of the components and the runs or connections between components. The software program normally does this in a manner intended to minimize the lengths of the normal operational connections between components, rather than the lengths of the scan connections. Consequently, the scan connections between successive flip-flops in the chain may be relatively long. The length of each such scan connection represents a capacitance which must be switched between logic states each time there is a change in the logic state of the output of the flip-flop driving that scan connection. This has certain ramifications, particularly where the circuit is implemented in CMOS.
For example, the capacitance of a relatively long scan connection will slow down the speed at which a flip-flop can switch the logical state of the signal on that connection, which represents an undesirable propagation delay for that signal. In addition, switching the state of that scan connection requires the dissipation of power, due to the capacitance. During a normal mode, when the scan connection is being ignored, the additional power required to switch the scan connection represents wasted power. Wasted power is always undesirable, but it is particularly undesirable where the circuit is powered by a battery, for example in a situation where the circuit is part of a portable computer.
A further consideration is that, since the scan connections directly interconnect respective scan flip-flops without any intervening circuitry, there is a risk of a race condition due to skewed clock signals. Such a race condition occurs where a first flip-flop is clocked and the resulting change in its output signal propagates across a scan connection to a second flip-flop before the second flip-flop is clocked.
One known technique for addressing some of these problems involves the provision of a scan flip-flop which has both a normal data output and a separate scan data output. The scan data output of each flip-flop is used to drive the scan connection to the next flip-flop in the chain, whereas the normal data output is used to effect normal operational connections for that flip-flop. Since the normal data output no longer drives the relatively long scan connection, it can switch states more quickly, thus reducing propagation delays. Further, the flip-flop may be intentionally designed with a discrete propagation delay for the scan data output, so that the scan data output switches states slightly later than the normal data output. This avoids a race condition across a scan connection, by ensuring that a change in the state of the signal at the scan data output is delayed somewhat after the clock edge which triggered the change, so that a flip-flop at the remote end of the scan connection will be clocked before the signal supplied across that scan connection can change states.
This known variation of the scan flip-flop reduces or avoids the problem of propagation delay in the operational signal, and the problem of a race condition in the scan connection. These known flip-flops have thus been adequate for their intended purpose. However, they have not been satisfactory in all respects. In particular, the separate scan outputs from these flip-flops still switch states in both the normal mode and the scan mode. Consequently, in the normal mode, the signals on the scan connections are changing states even though they are being ignored, which represents an unnecessary waste of power. With respect to correction of this problem, it is necessary to bear in mind that any circuitry added to reduce power consumption will itself consume power, and thus must reduce power consumption in the rest of the circuit by an amount which is greater than its own power consumption, in order to realize a net reduction in power consumption. Further, the area required on an integrated circuit for this additional circuitry should be minimal.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a
Brady III W. James
Lamarre Guy J.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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