Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2005-01-11
2005-01-11
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S500000, C713S501000, C713S503000, C713S600000, C714S700000, C714S719000, C714S721000, C711S170000, C711S167000, C711S105000, C365S233100
Reexamination Certificate
active
06842864
ABSTRACT:
A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.
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Barth Richard M.
Bystrom Todd W.
Davis Paul G.
Hampel Craig E.
May Bradley A.
Kim Hong
Rambus Inc.
Vierra Magen Marcus Harmon & DeNiro LLP
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