Method and apparatus for configuring a clock timing feedback...

Details Method and apparatus for configuring a clock timing feedback... Method and apparatus for configuring a clock timing feedback...

2006-05-23

2006-05-23

Cottingham, John R. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

Reexamination Certificate

active

07051224

ABSTRACT:
The present invention provides a method and apparatus for configuring a timing feedback path in a semiconductor device. The apparatus includes an oscillator adapted to provide a reference clock signal. The apparatus further includes at least one buffer layer adapted to receive the reference clock signal and provide a delayed clock signal, a selector adapted to select one of the delayed clock signal and the reference clock signal, and a device adapted to provide an output clock signal such that the selected one of the delayed clock signal and the reference clock signal is substantially in phase with the reference clock signal.

REFERENCES:
patent: 5812832 (1998-09-01), Horne et al.
patent: 6081905 (2000-06-01), Larsson et al.
patent: 6515519 (2003-02-01), Miyazaki et al.
patent: 2003/0098730 (2003-05-01), Miyazaki et al.
patent: 2003/0137360 (2003-07-01), Wang et al.

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