Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-03-27
2007-03-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000, C714S726000, C365S194000
Reexamination Certificate
active
10684280
ABSTRACT:
An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.
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Micro)n Technology, Inc.
Wong Cabello Lutsch Rutherford and Brucculeri LLP
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