Method and apparatus for complete hiding of the refresh of a sem

Details Method and apparatus for complete hiding of the refresh of a sem Method and apparatus for complete hiding of the refresh of a sem

1998-10-01

1999-12-07

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Data refresh

365 49, G11C 700

Patent

active

059994746

ABSTRACT:
A method and apparatus for handling the refresh of a DRAM array or other memory array that requires periodic refresh operations. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. The apparatus includes a multi-bank DRAM memory and an SRAM cache that stores the most recently accessed data. Each of the DRAM banks is operated with independent control, thereby enabling parallel refresh operations and read-write accesses to different banks. The capacity of the SRAM cache is selected such that refresh operations can be carried out even under the condition of indefinite 100% access of the multi-bank DRAM memory.

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Kazushige Ayukawa et al., IEEE Journal of Solid-State Circuits, "An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM's", IEEE J, vol. 33 (No. 5), (May, 1998).

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