Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-03-26
2001-07-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06255125
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the lithographic patterning of a semiconductor wafer. In particular, the present invention relates to a method and apparatus for forming and measuring structures on a test wafer which allows for more accurate prediction of line width variations which occur during manufacture of a final production wafer.
BACKGROUND OF THE INVENTION
Referring initially to
FIG. 1
a
, integrated circuits are formed on semiconductor wafers
10
typically made from silicon. The wafers
10
are substantially round and typically have a diameter of approximately 15 to 20 cm. Each wafer
10
is divided up into individual circuit die
15
which contain an integrated circuit. Since a single integrated circuit die
15
is often no more than 1 cm
2
, a great many integrated circuit die
15
can be formed on a single wafer
10
. After the wafer
10
has been processed to form a number of integrated circuit die on its surface, the wafer
10
is cut along scribe lines
20
to separate the integrated circuit die for subsequent packaging and use.
Formation of each integrated circuit die on the wafer is accomplished using photo-lithography. In general, lithography refers to processes for pattern transfer between various media. The basic photo-lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the photomask.
Referring to
FIG. 1
b
, during an intermediate stage in the manufacturing cycle, the wafer
10
is shown to include a film
25
which overlies the wafer
10
and a resist
30
disposed on the film
25
. Exposing the resist
30
to light or radiation of an appropriate wavelength through the photomask causes modifications in the molecular structure of the resist polymers to allow for transfer of the pattern from the photomask to the resist
30
. The modification to the molecular structure allows a resist developer to dissolve and remove the resist in exposed areas, presuming a positive resist is used. If a negative resist is used, the developer removes the resist in the unexposed areas.
Referring to
FIG. 1
c
, once the resist
30
on the wafer has been developed, one or more etching steps take place which ultimately allow for transferring the desired pattern to the wafer
10
. For example, in order to etch the film
25
disposed between the resist
30
and the wafer
10
, an etchant is applied over the patterned resist
30
. The etchant comes into contact with the underlying film layer by passing through openings
35
in the resist formed during the resist exposure and development steps. Thus, the etchant serves to etch away those regions of the film layer which correspond to the openings in the resist, thereby effectively transferring the pattern in the resist to the film layer as illustrated in
FIG. 1
d
. In subsequent steps, the resist is removed and another etchant may be applied over the patterned film layer to transfer the pattern to the wafer or to another layer in a similar manner.
Presently, there are a variety of known techniques for transferring a pattern to a wafer using photolithography. For instance, referring to
FIG. 2
, a reduction step-and-repeat system
50
(also called a reduction stepper system
50
) is depicted. The reduction stepper system
50
uses refractive optics to project a mask image onto a resist layer
30
. The reduction stepper system
50
includes a mirror
55
, a light source
60
, a filter
65
, a condenser lens system
70
, a mask
75
, a reduction lens system
80
, and the wafer
10
. The mirror
55
behaves as a collecting optics system to direct as much of the light from the light source
60
(e.g. KrF laser, ArF laser, mercury-vapor lamp, etc.) to the wafer
10
. The filter
65
is used to limit the light exposure wavelengths to the specified frequencies and bandwidth. The condenser system
70
focuses the radiation through the mask
75
and to the reduction lens system to thereby focus a “masked” radiation exposure onto one of the circuit die
15
.
The reduction stepper system
50
, projects an image onto a portion of the wafer
10
corresponding to a number of the individual circuit die
15
. This image is then stepped and repeated across the wafer
10
in order to transfer the pattern to the entire wafer
10
(and thus the name “stepper”). Current reduction stepper systems
50
utilize masks that contain a pattern that is an enlargement of the desired image on the wafer
10
. Consequently, the mask pattern is reduced when projected onto the resist
30
during exposure (and thus the name “reduction stepper”).
With an ever increasing number of integrated circuit patterns being formed on a circuit die, the importance of properly designing patterns to form structures that are isolated and non-interfering with one another has also increased. Accordingly, when designing a pattern to place on a mask, it is of significant benefit to know in advance the amount of error to expect with respect to the corresponding structures formed on the wafer so that such error can be accounted for in advance. For example, devices such as a microprocessor formed on the semiconductor wafer often will be limited by the transistor providing the slowest speed. As the speed of a transistor can vary significantly as a result of line width variations, it is desirable to know in advance how the transistors formed at various locations in the stepper field will be affected by various processing steps so that such variations can be properly accounted for.
Prior to manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various circuit components. While it is possible to estimate line width variations on the structures formed on the test wafer in order to predict the amount of line width variations to expect of corresponding structures formed on the final production wafer, such estimates have often shown to deviate from the actual line width variations which occur. Thus, if inaccurate line width corrections are made based on such estimates, this in turn can lead to slower device processing speeds as compared to a device produced in which all line width variations are properly compensated for in advance.
Accordingly, there is a strong need in the art for a method of accurately predicting what effect the various processing steps will have on line width variations of structures formed throughout an imaging field.
SUMMARY OF THE INVENTION
Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various circuits. Each test wafer includes a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insulating layer. The film layer is comprised of, for example, poly-silicon and has a predetermined thickness which substantially corresponds to the thickness of a film layer deposited on the final production wafer.
An anti-reflective coating is formed over the film layer and a photo-resist is formed over the anti-reflective coating. The anti-reflective coating and photo-resist are used to etch a desired pattern in the film layer. Once etched, the film layer is implanted with a dopant to diffuse dopant atoms throughout. Thereafter, line width measurements of the etched pattern are taken using conventional electrical line width measurement techniques or the like. Variations found in the line width measurements from desired line width measurements are then compensated for prior to manufacturing the final production wafer so as to provide circuits with faster processing speeds. For example, line width variations found with respect to certain structures on the test wafer may be compensated for by varying the design of the pattern formed on the reticle prior manufacture of the final production wafer.
By using a semi-conductive film layer and implanting the film layer with a conductive dopant only after etching, the test wafers of the present inventio
Minvielle Anna M.
Nguyen Khanh B.
Plat Marina V.
Schmidt Regina T.
Spence Christopher A.
Advanced Micro Devices , Inc.
Luk Olivia T
Niebling John F.
Renner Otto Boisselle & Sklar
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