Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-03-02
2001-06-12
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
06247154
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and apparatus for testing sequential circuits with delay fault built-in self test (BIST) with partial scan insertion that can be combined with stuck-at fault testing.
2. Description of the Related Art
One conventional approach to testing digital electronic circuits is stuck-at fault testing. Many techniques have been used for stuck-at fault testing. Typically, stuck-at fault testing is accomplished by successively applying a set of test vectors to the input of a digital circuit to cause the circuit to generate a known response under normal operating conditions. If one or more stuck-at faults exist in the circuit, the response of one or more of the test vectors will differ from the known response. Stuck-at fault testing is useful for revealing many types of faults, however, this type of testing does not reveal path-delay faults.
A path delay-fault occurs when a circuit response requires more time than specified by design requirements of the circuit. The delay of a digital circuit is the maximum time needed for outputs of the circuit to be determined after inputs to the circuit have changed. Signal transitions can travel through paths from primary inputs, gates or flip-flop outputs to primary outputs or flip-flop inputs of the circuit. For example, a path delay-fault (PDF) models when the cumulative delay of propagating a transition along a path of the circuit exceeds a predetermined limit. The predetermined limit can be a clock period. Delay-fault testing can be used to check if the circuit meets the required clock rate or speed requirements by detecting PDFs in the circuit.
U.S. Pat. No. 5,422,891, ('891) issued to one of the inventors of this disclosure, describes a method for robust delay fault built-in self-testing of combinational integrated circuits. Combinational circuits include inputs, outputs and logic gates. Robust delay testing is used to test for an excessive path delay of a tested path independently of other path delays in the circuit. In the method, hazardous nodes of the IC are determined. A hazardous node is a gate whose output momentarily switches from the correct output for a brief time period. Cut-points are inserted in the circuit to divert input to hazardous nodes to an observation point. An output multi-input signature register (MISR) at the observation point generates a first signature. An output MISR provides a second signature for outputs to the IC. During testing, a hazard-free input pattern is applied to the IC and the generated first and second signatures are compared to known correct signatures.
In the '891 patent it is disclosed that an example of a hazardous node which is a reconvergent fanout circuit. Reconvergent fanout circuit splits into at least two paths before it reconverges at another point in the circuit. Signal parity can be defined as the number of inversions a signal is subject to as it travels along a path. A reconvergent fanout circuit can have a hazard if the paths are of opposite signal parity. For example, output paths from a NAND gate can reconverge at an OR gate. One of the paths is inverted with an inverter to produce odd signal parity on the path. The other path from a NAND gate has even signal parity. A hazard can occur at hazardous node the OR gate since one path has opposite signal parity to the other path. Either path can be cut to avoid a hazard at hazardous node. If there are more than two paths reconverging, than either all odd parity paths or all even parity paths can be cut. Accordingly, XOR and equivalence gates are modified such that a first path is inverted and a second path is non-inverted for eliminating hazards on the gates. Alternatively, hazardous nodes can be eliminated during testing for eliminating opposite parity at the hazardous node during testing.
Circuits can also include sequential elements such as flip-flops. A sequential delay test can use a pair of vectors to start a signal transition down a path, propagate the transition along a path and allow fault observation at the path end. Scan testing has been used to test sequential circuits is by inserting scan chain hardware on all flip-flops of the circuit. In scan mode, all flip-flops behave similar to a shift register, such that the memory in the circuit can be serially scanned out through a pin on the chip. This method has the disadvantage of adding hardware to each flip-flop on the chip. The additional hardware creates added expense and power requirements of the circuit. Also, scan testing is slow because of the shifting of the scan chain in and out of the chip.
Other techniques have been disclosed for detecting delay faults along a signal path within a sequential digital circuit which do not use a full-scan. U.S. Pat. No. 5,502,647 describes partial scan testing of sequential circuits. In this partial scan methodology flip-flops are selected such that the minimum feedback vertex set (MFVS) of a flip-flop dependency graph of all loops, except self-loops, are broken. The MFVS of the circuit, i.e. the minimum quantity of gates whose removal makes the circuit acyclic, is a lower bound and in many cases is significantly smaller than the MFVS of the flip-flop dependency graph. Flip-flops are repositioned so that, in a modified circuit, every circuit MFVS gate drives one flip-flop that can be scanned. Resynthesis and retiming is used to transform any circuit into an equivalent circuit whose flip-flop dependency graph MFVS is equal to the MFVS of the original circuit.
U.S. Pat. No. 5,365,528 describes a method for testing delay faults in non-scan sequential circuits. In this method, in order to detect a delay fault along a signal path of interest in a sequential digital circuit, a source flip-flop and a destination flip-flop, proximate the beginning and end of the path, respectively, are designated in the circuit. Next, the signal path is activated to establish what logic values are necessary at the input of each of a set of combinational elements in the path to propagate a selected signal transition from the source flip-flop to the destination flip-flop. A first and second backward justification process is carried out to synthesize a first sequence to propagate a selected logic value from a primary circuit input to the source flip-flop to cause it to generate the selected signal transition to propagate to the destination flip-flop. A second backward justification process is carried out to synthesize a second vector sequence which serves to propagate the value latched in the destination flip-flop to a primary output. The vectors of the first and second sequences are then applied at periodic intervals using a slow clock, except that the rated clock is applied to the last vector of the first sequence to propagate the logic value affected by the delay fault ultimately to the primary output. By comparing the value propagated to the primary output to the expected correct logic value, a determination can be made as to the existence of a delay fault.
It is desirable to provide a method and system for reliable testing of path delay faults of sequential circuits with minimal hardware.
SUMMARY OF THE INVENTION
Briefly described, the present invention comprises a method and apparatus for combined stuck fault testing and partial scan delay-fault built-in self testing (BIST). For stuck fault testing, a succession of first input patterns are applied to the circuit for generating stuck-fault output responses. For example, the first input patterns can be generated by a linear feedback shift register. Stuck fault output responses are processed by a multi input signature register (MISR) to provide a first signature.
For partial scan delay-fault BIST, the circuit is modeled for breaking all flip-flop feedback cycles in the circuit. An optimal feedback vertex set is determined from an S-graph of the circuit corresponding to flip-flops to be scanned during testing to break all sequential cycles. A devour, digest and tidy up (DDT) heuristic can be used on a weighted signed graph
Bushnell Michael L.
Parthasarathy Ganapathy
Chung Phung M.
Mathews, Collins Shepherd & Gould P.A.
Rutgers The State University of New Jersey
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