Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-18
2005-01-18
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S057000, C714S031000
Reexamination Certificate
active
06845478
ABSTRACT:
Disclosed is a method of testing memory, comprising providing one or more semiconductor wafers having one or more semiconductor chips thereon, each said chip comprising one or more memory cells, providing a programmable testing apparatus comprising at least one test pattern generators and a test bed adapted to receive said one or more wafers in communicative contact so as to address individual memory cells, chips, and wafers and transmit information thereto and receive information therefrom, receiving one or more test commands, constructing a test sequence of one or more commanded tests from said test commands, constructing at least one header comprising location information for each said wafer, chip and memory cell, testing said memory cells with a test pattern generated by said test pattern generator, collecting the results of said testing and passing them to a display device, passing said location information to said display device, constructing and displaying a graphical representation of said test results using said location information.
REFERENCES:
patent: 6000048 (1999-12-01), Krishna et al.
patent: 6421798 (2002-07-01), Lin et al.
patent: 6449741 (2002-09-01), Organ et al.
patent: 20020042897 (2002-04-01), Klein et al.
Brinks Hoffer Gilson & Lione
Infineon Technologies Richmond LP
Tu Christine T.
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