Method and apparatus for checking cache coherency in a computer

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711142, 711143, 711144, 711146, 712 1, 712 32, G06F 934

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06049851&

ABSTRACT:
A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

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