Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1997-06-13
2002-06-18
Le, Dieu-Minh (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06408410
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of integrated circuits and, more specifically, the present invention relates to testing of buffer circuits in integrated circuits.
2. Background Information
Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As integrated circuit features continue to shrink, test costs relentlessly rocket skyward. Greater numbers of interface nodes, higher operating frequencies and specialized packaging arrangements such as multi-chip modules all contribute to soaring test costs.
To reduce the possibility of delivering defective chips to customers, testing is performed on integrated circuit dies prior to shipping. Equipment for testing integrated circuits increases in cost and complexity as die contacts decrease in size and increase in number. Indeed, the cost of exhaustive testing of every interface node of an integrated circuit is prohibitive. Unfortunately, saving costs by reducing testing may result in an increased probability of defective chips being sold to customers.
Output buffers and input/output buffers are features of an integrated circuit that typically must be thoroughly tested prior to sale. In order to identify speed related defects, these buffers are generally verified with test equipment that skews the relative relation between data signals and a clock or strobe signal until a failure is detected. Use of test equipment of this nature is generally very expensive, difficult to maintain and hard to use. With the continuing effort to increase integrated circuit speeds, the identification of speed related defects in integrated circuit input and output buffers with prior art test equipment may become a prohibitively challenging task because of the speed limitations associated with present day tester technology.
As will be seen, one embodiment of the present invention provides a built in self-test of integrated circuit input and output buffers for speed related defects without the use of expensive test equipment.
SUMMARY OF THE INVENTION
A method and an apparatus for self-testing a buffer circuit is disclosed. In one embodiment, an oscillating feedback loop is created between an output of a buffer circuit and an input of the buffer circuit. A rate of oscillation is then measured in the feedback loop to identify a speed related defect in the buffer circuit. Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Le Dieu-Minh
LandOfFree
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