Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-11
2007-09-11
Tu, Christine T. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
10785826
ABSTRACT:
An integrated circuit device (200) can include a main portion (204) and a built-in self-test (BIST) portion (204) having outputs coupled to physical input structures (e.g., bond pads) (206) of the integrated circuit device (200). A BIST portion (202) can test timing critical parameters that take into account the effect of input structures (206). A BIST portion (202) can apply BIST test signals with a pipeline structure that can emulate timing parameters, such as a set-up time (Ts) and a clock-to-output time (Tco).
REFERENCES:
patent: 5822228 (1998-10-01), Irrinki et al.
patent: 5912901 (1999-06-01), Adams et al.
patent: 6078637 (2000-06-01), Ansel et al.
patent: 6671842 (2003-12-01), Phan et al.
patent: 6675336 (2004-01-01), Thakur et al.
patent: 6681359 (2004-01-01), Au et al.
patent: 6738938 (2004-05-01), Nadeau-Dostie et al.
WEBSTER'S II New Riverside University Dictionary, “couple”, The Riverside Publishing company, 1984.
Li Jun
Tran Thinh
Tzou Joseph
Cypress Semiconductor Corporation
Haverstock & Owens LLP
Tu Christine T.
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