Method and apparatus for building up large scale on chip...

Details Method and apparatus for building up large scale on chip... Method and apparatus for building up large scale on chip...

2006-01-03

2006-01-03

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S393000

Reexamination Certificate

active

06982197

ABSTRACT:
The apparatus and method for forming de-coupling capacitors on top of SOC VLSI chip. The introduced large amount of de-coupling capacitor is intended to solve the power delivery problem of highly integrated and powered VLSI chip, especially in the Silicon-On-Insulator (SOI) technology. This invention proposes a design scheme which could utilize virtually unused area to build efficient de-coupling capacitors without introducing additional manufacture cost. This design scheme is especially effective when the VLSI technology is scaled down further.

REFERENCES:
patent: 4410905 (1983-10-01), Grabbe
patent: 5656834 (1997-08-01), Grzyb et al.
patent: 6496053 (2002-12-01), Daubenspeck et al.
patent: 6653681 (2003-11-01), Appel
patent: 6830650 (2004-12-01), Roche et al.

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