Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
2007-02-20
2007-02-20
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S220000, C712S229000
Reexamination Certificate
active
10757256
ABSTRACT:
A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. The performance indicators and counter values may be used as a mechanism for identifying cache hits and cache misses. Performance counters are incremented each time the instructions of routines of interest are executed and each time the instructions must be reloaded into the cache. From the values of these counters the cache hit-miss ratio may be determined. When the cache hit-miss ratio becomes less than a predetermined threshold, i.e. a greater number of cache misses than cache hits, the present invention may determine that a problem condition has occurred and initiate “chase tail” operations for avoiding overwriting of entries in the cache.
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DeWitt, Jr. Jimmie Earl
Levine Frank Eliot
Richardson Christopher Michael
Urquhart Robert John
Fleming Fritz
Lai Vincent
Lammes Francis
Rodriguez Herman
Yee Duke W.
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