Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-01
2008-10-14
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C713S503000
Reexamination Certificate
active
07437636
ABSTRACT:
Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. Some of the disclosed schemes are also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. In particular embodiments, the loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. In certain embodiments, only the capture cycle is performed at the corresponding system timing. In some embodiments, a programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.
REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4912340 (1990-03-01), Wilcox et al.
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5386392 (1995-01-01), Cantiant et al.
patent: 5524114 (1996-06-01), Peng
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5640539 (1997-06-01), Goishi et al.
patent: 5680543 (1997-10-01), Bhawmik
patent: 5717700 (1998-02-01), Crouch et al.
patent: 5717702 (1998-02-01), Stokes et al.
patent: 5726995 (1998-03-01), Wong
patent: 5740182 (1998-04-01), Narain
patent: 5805608 (1998-09-01), Baeg et al.
patent: 5812561 (1998-09-01), Giles et al.
patent: 5867507 (1999-02-01), Beebe et al.
patent: 6014763 (2000-01-01), Dhong et al.
patent: 6023778 (2000-02-01), Li
patent: 6055658 (2000-04-01), Jaber et al.
patent: 6145105 (2000-11-01), Nadeau-Dostie et al.
patent: 6178532 (2001-01-01), Pierce et al.
patent: 6199182 (2001-03-01), Whetsel
patent: 6256760 (2001-07-01), Carron et al.
patent: 6286119 (2001-09-01), Wu et al.
patent: 6327684 (2001-12-01), Nadeau-Dostie et al.
patent: 6330681 (2001-12-01), Cote et al.
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 6763489 (2004-07-01), Nadeau-Dostie et al.
“Built-in Self-Test Technique for Speed Sorting of VLSI Chips,”IBM Technical Disclosure Bulletin, vol. 32, Issue 8B, 2 pp. (1990).
Kim et al., “Multi-Frequency, Multi-Phase Scan Chain,”IEEE International Test Conference, pp. 323-330 (1994).
Nadeau-Dostie et al., “ScanBist: A Multifrequency Scan-Based BIST Method,”IEEE Design&Test of Computers, pp. 7-17 (1994).
Nadeau-Dostie et al., “ScanBist: A Multi-frequency Scan-Based BIST Method,”Proc. ITC, pp. 506-513 (1992).
Tendolkar et al., “At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC™ Microprocessor,” 6 pp. (also published as Tendolkar et al., “At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC™ Microprocessor,”VLSI Test Symp., pp. 3-8 (2000)).
“Test Facility for Large Scale Computers,”IBM Technical Disclosure Bulletin, vol. 13, Issue 6, 2 pp. (1970).
Hassan Abu
Rajski Janusz
Tamarapalli Nagesh
Thompson Robert
Britt Cynthia
Klarquist & Sparkman, LLP
Tabone, Jr. John J.
LandOfFree
Method and apparatus for at-speed testing of digital circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for at-speed testing of digital circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for at-speed testing of digital circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4012002