Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-02-22
2009-11-10
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C714S032000, C714S700000, C714S714000, C714S719000, C714S723000, C714S724000, C714S726000, C714S731000, C714S735000, C713S500000, C713S501000, C702S069000, C702S075000, C702S106000, C702S108000, C702S117000, C324S364000, C324S160000
Reexamination Certificate
active
07617431
ABSTRACT:
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.
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Fujitsu Limited
Staas & Halsey , LLP
Trimmings John P
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