Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-23
2003-03-04
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S233100
Reexamination Certificate
active
06530051
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to apparatus for measuring a logic state of a controller of, for example, a Dynamic Random Access Memory (DRAM) and, more particularly, to circuitry that allows for the easy identification of the State in a state diagram being used by the DRAM controller that is used to control a DRAM generator system.
BACKGROUND OF THE INVENTION
Modern Dynamic Random Access Memory (DRAM) chips have many different voltages (e.g., more than 10) on-chip that have to be generated by a plurality of generator circuits. These voltages include several reference voltages (e.g., for receiver circuits and for bias current generation) as well as several voltages that supply various functional blocks on the chip with operating current (e.g., voltages for sense amplifiers and word line drivers). All of these voltages are generated from one external source voltage by the plurality of generator circuits.
There are basically three operating modes which occur for the voltage generating circuits. These modes are (1) a normal operating phase, (2) a test and burn-in phase, and (3) a power-on phase. In each of these modes the generator system operates in a different way, and needs to be controlled in a specific way. A controller for the generator system has to ensure a proper coordination of all generator functions for each of the various modes. More particularly, once the external source voltage (VEXT) is applied to the DRAM chip, the generator system goes through a power-on phase. After the power-on phase, all voltages on the DRAM chip are stable, and the generator system (and the whole chip) enters the normal operating phase. For burn-in and for test purposes, a multitude of additional functions have to implemented into the generator system.
The problem is that the overall logic behavior of the generator system, and its controller, is relatively complex. This is especially true during a late phase of a design project as all of the sub-systems are being put together, and it is very likely that changes in the logic functionality of the controller have to be made. In a current one-Gigabit (GB) chip, known by the designation ZEUS DD1, logic control functions of a generator system therein are ere clearly separated from the voltage generating functions. The logic behavior of the generator system is implemented in a digital controller (a finite state machine). In order to realize a finite state machine, design and layout synthesis is used in the one-GB Dynamic Random Access Memory (DRAM) chip. The logic behavior therein is specified in a truth table, and the concept was to create circuitry automatically within a short time by using the respective software tools. Thus, changes or corrections of the controller could theoretically be performed within a few hours, even in a late stage of a project.
Still further, for characterization and debugging of the generator system, it is very valuable to have access to the state information. Being able to read out the controller states allows for an easy identification of controller errors and problems in the generator system. This is especially helpful during the power-on sequence when the controller sequentially turns on all generator sub-systems but always has to wait for confirmation signals from one sub-system before it can turn on a next sub-system. If, for example, the power-on sequence does not finish, it can easily be determined from the controller's state what the problem is (e.g., the controller is waiting for a VPP (pump voltage) limiter signal that indicates that the VPP has reached a predetermined level) if such controller diagnosis technique were available. The problem is that it is not always practical to measure all internal nodes by pico-probing since not all internal-nodes can be connected to a last metal layer on which probe pads are formed. Also, pico-probing requires a lot of experience and time for each individual measurement. Therefore, such method is not suitable for obtaining “mass data”. Still further, if the controller uses a 1-out-of-N coding, each analysis requires the probing of approximately 50 probe points which is very impractical.
Additionally, problems in existing solutions are that both design and layout synthesis tools do not provide a required solution to many problems for providing a flexible and fast controller design. For example, the design synthesis tool demands a large amount of time for learning the handling and functionality of the tool, and this tool also made manual corrections and working around of problems necessary. The layout synthesis tool created results that contained errors and required manual inspections and corrections. Additionally, one could not provide timing constraints to inputs to the tool for generating certain voltages. This required manual checks of a synthesized layout for a critical path which then required manual corrections. Therefore, it is desirable to provide a technique where changes in the logic behavior of the controller is obtainable in a systematic and very quick manner.
The present invention provides a controller circuit for a generator system that is very flexible so that its functionality can easily be adjusted to a specific generator system to allow for last minute changes of the behavior of a generator circuit, and includes circuitry for debugging purposes to provide a simple method to read out the state information of the controller.
SUMMARY OF THE INVENTION
The present invention is directed to a controller circuit for a generator system located on a chip such as a Dynamic Random Access Memory (DRAM). The specific behavior of the present controller circuit is made very flexible so that its functionality can easily be adjusted to the specific associated generation system and permit quick “last-minute-changes” in the controller circuit's behavior, and includes state identification circuitry for debugging purposes to provide a simple method to read out the state information of the controller.
Viewed from one aspect, the present invention is directed to a controller for controlling a generator system on a memory chip, the controller operating as a state machine in accordance with a state diagram including a plurality of N states. The controller comprises a state storage device, and state identification circuitry. The state storage device is responsive to input signals including a 1-out-of-N code indicating a change in the state diagram from a current state to a next state of the plurality of N states for generating a revised plurality of N state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of N states. The state identification circuitry is responsive to a selectively applied activation signal for inhibiting the output of the revised plurality of N state signals from the state storage device and sequentially reading out the plurality of N state signals including the 1-out-of-N code currently stored in the state storage device. The 1-out-of-N code which is read out from the state storage device is used to indicate which state of the state diagram the controller is presently in when the controller fails to complete a procedure in the state diagram.
Viewed from another aspect, the present invention is directed to controller for controlling a remote system on a memory chip which operates in accordance with a state diagram including a plurality of N states. The controller comprises an evaluation arrangement, a state storage device, state identification circuitry, and an output arrangement. The evaluation arrangement is responsive at any instant of time for evaluating only one of a plurality of N input signals to the controller from remote devices in relation to only one of a plurality of N state signals. The evaluation arrangement generates one of a plurality of Y output signals that has a predetermined logical value for entering a next state in the state diagram when a condition has been met wherein the one state signal and the one input signal have met predetermined logical co
Abraham Esaw
DeCady Albert
Infineon - Technologies AG
Stanton Braden
LandOfFree
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