Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-05-30
2006-05-30
Torres, Joseph (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
07055083
ABSTRACT:
A method and apparatus for allocating CRC (Cyclic Redundancy Check) codes in a flash ROM (Read-Only Memory). The apparatus includes a flash ROM and a microprocessor. The flash ROM is logically divided into a plurality of data blocks. Each data block contains a CRC code block that includes a plurality of bytes for saving CRC codes. The microprocessor can write to and read from the flash ROM, calculate a complement code of a sum of all the bytes of the data block, and add the complement code to data of one of the plurality of bytes. The microprocessor thus generates new CRC codes and writes them to the corresponding CRC code block. The new CRC codes generated can meet the critical requirement of CRC. That is, the sum of all the bytes of the data block (including the CRC code block) is null.
REFERENCES:
patent: 5459850 (1995-10-01), Clay et al.
patent: 5951707 (1999-09-01), Christensen et al.
Chung Wei Te
Hon Hai - Precision Ind. Co., Ltd.
Torres Joseph
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