Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-01-18
2009-08-25
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
07581151
ABSTRACT:
In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the resource was not part of the original design and state diagram of the unmodified state machine. In one embodiment, a method and apparatus is provided for dynamically reconfiguring a plurality of test circuits in re-useable modules on an IC without modifying the controller state machine in the re-usable module.
REFERENCES:
patent: 5189675 (1993-02-01), Nozuyama et al.
patent: 5228045 (1993-07-01), Chiles
patent: 5325368 (1994-06-01), James et al.
patent: 5343478 (1994-08-01), James et al.
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5377198 (1994-12-01), Simpson et al.
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5477548 (1995-12-01), Beenker et al.
patent: 5592024 (1997-01-01), Aoyama et al.
patent: 5677916 (1997-10-01), Nozuyama
patent: 6041176 (2000-03-01), Shiell
patent: 6073254 (2000-06-01), Whetsel
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6311302 (2001-10-01), Cassetti et al.
patent: 6334198 (2001-12-01), Adusumilli et al.
patent: 6378090 (2002-04-01), Bhattacharya
patent: 6385749 (2002-05-01), Adusumilli et al.
patent: 6405335 (2002-06-01), Whetsel
patent: 6631504 (2003-10-01), Dervisoglu et al.
patent: 6754863 (2004-06-01), Grannis, III
patent: 6760876 (2004-07-01), Grannis, III
patent: 6813739 (2004-11-01), Grannis, III
patent: 6961884 (2005-11-01), Draper
Whetsel, “An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores,” IEEE Inrenational Test Conference, Paper 3.3, pp. 69-78 (1997).
Bruce William C.
Moyer William C.
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Susan C.
Torres Joseph D
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