Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
1997-12-30
2001-10-23
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C345S505000, C345S547000, C345S571000, C348S236000, C348S715000, C382S304000
Reexamination Certificate
active
06307588
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the processing of image data stored in a plurality of parallel random access memories (RAMs) and more particularly to a method and apparatus for accessing multiple identical copies of the image data.
BACKGROUND OF THE INVENTION
In machine vision applications, it is common to acquire image data related to the surface of a workpiece and to store this data for further processing. Stored image data is used for pattern-recognition, error detection and other surface inspection applications.
FIG. 1
details a basic image processing arrangement according to the prior art. A camera
30
having a lens
32
for acquiring an image and an electro-optical pickup device, such as a CCD array
34
, transmits image data over a data line
36
to a memory device
38
. The memory device in this example comprises a random access memory (RAM) configured to receive image data. Data is typically provided in digital form, often following conversion from an analog form by a analog to digital converter (not shown) located in the data path between the CCD array and the image RAM
38
. Image data is stored in the image RAM
38
as individual pixels that each represent a given segment of the overall image. Each pixel represents a relatively small part of the total image, such that in aggregate, the image appears relatively continuous. Each pixel has a discrete intensity value that defines a brightness and, when applicable, a shade of color. Where the image is acquired and recorded in color, a pixel may be formed from at least three different-color sub-pixels that form the overall color shade. Alternatively, where the image is monochromatic, a numerical grayscale intensity value is recorded for the pixel. As described further below, the RAM is organized as a series of rows and columns, each individually addressed by an incoming data line. By addressing the appropriate row and column, all or part of a particular pixel intensity value can be accessed and read. An image processor
40
that can comprise any acceptable microprocessor or application specific integrated circuit (ASIC) retrieves intensity values as data over a multi-bit data line
42
based upon input pixel addresses transmitted over a multi-bit address line
44
. Model or “template” image data, representative of an image to be compared to the acquired image, can be input to the processor through a variety of input lines denoted generally as the input line
48
. The processor matches the model data to the acquired data stored in the RAM
38
. The processor, using known techniques, calculates an overall match of the acquired data with the known data by combining the results of each individual pixel-by-pixel match performed by the processor. Results of matches made by the processor are output on an output line
50
to other processors or computers. These processors utilize the output data to perform more advanced operations such as overall pattern recognition.
The image processing arrangement of
FIG. 1
enables pixel data to be accessed in the RAM in a largely serial manner. That is, only one pixel data can be read from the RAM to the processor in each addressing cycle. Some microprocessor arrangements such as the well-known Pentium® MMX® microprocessor available from Intel Corp. can access several pixel data simultaneously. For example the forenamed microprocessor uses a single address to access eight sequential eight-bit pixel data in one clock cycle. However, this arrangement has a limitation in that it requires all pixels data to be stored adjacent to each other in the RAM. Hence, to process a group of pixels widely spaced in two dimensions of an image, or at remote spacings from each other, the processor must address pixel data over several clock cycles. This slows the image processing procedure. Speed is a concern in a high-speed machine vision environment in which a large volume of data must be managed by the processing system continuously.
It is, therefore, an object of this invention to provide a more efficient method and apparatus for accessing multiple pixels in an image processing memory array.
SUMMARY OF THE INVENTION
This invention overcomes disadvantages of the prior art by providing parallel access by an image processor to a set of image memory devices each having a similar or identical set of image pixel data stored therein at similar or identical memory addresses without requiring the image processor to independently address each of the memory devices. In particular, a group of identical pixel data are stored at identical addresses in each of the memories. In other words, the same pixel data can be accessed in each memory by applying the same address to each memory. Given this interrelationship between memories, and the pixel data stored within each of the memories, an address expander structure uses a function governing the relationship between pixel data in a group of pixel data to convert a predetermined “central” pixel address into a plurality of interrelated pixel addresses from the group. The interrelated addresses allow the processor to generate one address and, in turn, address several different pixel data in the group simultaneously—one pixel data from each of the plurality of memories. These pixel data are all provided to the processor at once. This method and apparatus enables fewer interconnections with memory components since the number of address lines needed by the processor is reduced.
In a preferred embodiment, one or more address expanders are employed to access memory locations in each of the memory devices that each contain a particular pixel data related to a selected “central” pixel data specifically addressed by the processor. As such, the addressing of a central pixel by the processor results in the addressing by the address expanders of a plurality of interrelated pixels each stored in different memory devices. Each interrelated pixel is therefore accessed concurrently by the processor. The address expanders use predetermined functions to generate a plurality of addresses offset from the central pixel address. Each of the plurality of offset addresses are transmitted by a dedicated address line from the expanders to a respective memory device. The processor moves through the image data selecting successive central pixels until all desired image data is addressed and successive offset addresses have been produced by the address expanders.
In a preferred embodiment the memory devices comprise a plurality of buffers each constructed from one or more RAMs organized as a series of addressable rows and columns. The address expanders comprise a row address expander that receives a row address of a central pixel from the processor and a column address expander that receives a column address of the central pixel from the processor. The row address expander and column address expander each generate several offset row and column addresses by performing a predetermined function to the input row and input column address of the central pixel.
In one embodiment, the predetermined function is the addition or subtraction of offset constants in order to access pixels that are directly adjacent to the central pixel within the overall image. Other functions, such as logarithmic or multiplicative functions can be employed by the address expanders to generate offset addresses in an alternate embodiment. The address expanders can comprise ASICs or field programmable gate arrays (FPGAs) that enable constants and/or functions to be entered into the expanders on an ongoing basis by a downstream data processor. The constants and/or functions can be varied based upon specific image processing requirements or based upon the nature of the central pixel (e.g. location of the central pixel in the overall image, its relative intensity, its color shade, etc.). In one embodiment the memory array includes twelve buffers each constructed of two 512 K-byte RAMs arranged in a ten-bit-by-ten-bit row and column address arrangement. The address expanders generate three rows and four columns to acces
Anderson Kurt M.
Hinz Robert C.
Olson Steven J.
Cognex Corporation
Garber Wendy R.
Loginov William
Vu Ngoc-Yen
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