Electrical computers and digital processing systems: support – Reconfiguration
Reexamination Certificate
1999-03-09
2001-02-27
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: support
Reconfiguration
C709S221000
Reexamination Certificate
active
06195750
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of computers and more particularly to multiprocessor systems having CPUs that can be added or removed from system operation.
Computer users are concerned about availability of their computer systems and particularly upgrades and downgrades in the CPU configuration. A CPU upgrade is performed, among other reasons, to increase the capacity of the computer system and a CPU downgrade is performed to reduce the capacity of the system. Increasing or decreasing the capacity of a system, besides tailoring the system to fit the data processing needs of the user, also has a significant cost element since many software products that run on computer systems are priced as a function of the system capacity.
In large multiprocessor computer systems that employ multiple system control programs (SCPs), CPU upgrades have been difficult to schedule because the computer user must plan an outage for all of the SCPs running on the CPU to be upgraded. With the continued exploitation of logical partitioning using multiple domain features (MDF), it has become impractical to schedule all SCPs to be down at the same time. This difficulty causes customers to delay necessary upgrades rather than attempting to schedule the total system outage. The current upgrade process includes the following steps:
1) Establish a hardware upgrade price with the hardware vendor.
2) Notify the Operating System Vendor (for example, IBM for main frame systems) to change their software charges to account for the upgraded system capacity.
3) Notify Independent Software Vendors (ISVs) to change their software charges to account for the upgraded system capacity and providing the new CPUID version code when necessary.
4) Update ISV software encoded CPUID tables.
5) Take a system outage to implement the upgrade
Steps 1-4 are normally performed days or even weeks before the outage is taken. While few software products actually check the CPUID version code for compliance, the customer is normally required by contract to notify both the Operating System vendor and any ISVs when their licensed software will be run on a different hardware configuration. The current practice often encounters delays that are wasteful to the computer user.
Accordingly, and in light of the problems of prior systems, there is a need to be able to upgrade computer CPU configurations dynamically without causing the computer user to suffer the delays and outages that have heretofore been required. It is desirable that users be able to purchase additional capacity quickly and with little effort.
SUMMARY OF THE INVENTION
The present invention is a multiprocessor system having a plurality of CPUs that can be dynamically reconfigured between online and offline without system shutdown. The multiprocessor system is operable in different modes, including a user mode for processing user programs and a system mode for processing system programs unavailable to users. Although the multiprocessor system is capable of being shutdown to terminate operation and permit reconfiguration during or after a shutdown, the multiprocessor system of the present invention includes a dynamic reconfiguration subsystem for reconfiguration without shutdown.
The dynamic reconfiguration subsystem includes a service processor having a feature file for identifying a current online number corresponding to a current number of online CPUs, a current offline number corresponding to a current number of offline CPUs and an update number corresponding to changes to be made in the current online number and the current offline number. A reconfiguration control unit is provided for reconfiguring CPUs in the multiprocessor system without being shutdown that includes a store for storing configuration code in response to the feature file, a system state execution unit for executing the configuration code to form configuration control information and decoder means for decoding the control information to change the current number of online CPUs and the current number of offline CPUs by the update number.
The present invention allows the definition of offline logical processors (LPs) which may be brought online when the reserved capacity is made available. The total number of domain LPs, including offline LPs, may not exceed the total number of physically installed CPUs. However, when the domain is activated, the number of online LPs per domain may not exceed the number of customer purchased non-ICS CPUs.
With the present invention, a user must still perform steps 1-4 above, as discussed in the background, but a system outage is not required. The steps performed are as follows:
1. Install new feature file on the SVP which defines the number of online CPUs.
2. Macrocode adjusts the number of online CPUs in the system to match the feature file.
3. Macrocode resets the fenced (Off-line) CPU.
4. Macrocode adds CPUs to the shared pool.
5. Macrocode dispatches work (domain/partition LPs) on the shared CPUs.
6. The LPCTL frame is used by the customer to change the number of dedicated LPs.
7. The customer can use the MVS command “CF CPU(nn), online”.
The actual upgrade process is controlled to return the correct CPUID including version code to the SCP when it is retrieved with the Store CPUI) (STIDP) instruction.
During SCP initialization, a STIDP instruction is performed to retrieve the CPUID and save it in storage. IBM SCPs such as OS/390 use this storage location to establish a unique dynamic path array identifier, determine recovery actions, and establish future Service Call Logical Processor (SCLP) actions. ISV software products (in particular those products that check their encoded CPUID tables for compliance) issue their own STIDP when that ISV software is initialized.
The CPUID contains each vendor's model number (for example, Amdahl 700) as well as a version code which identifies a specific server (for example, x‘58’=785). In the case of the Amdahl MGS 700, the X‘5’ indicates that the CPUs are running at full speed and the X‘8’ defines that eight physical CPUs are installed and available for customer use.
The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description in conjunction with the drawings.
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patent: 5530753 (1996-06-01), Easter et al.
patent: 5574936 (1996-11-01), Ryba et al.
patent: 5784636 (1998-07-01), Rupp
patent: 5784701 (1998-07-01), Greenstein et al.
patent: 5790880 (1998-08-01), Ireton
patent: 5819061 (1998-10-01), Glassen et al.
patent: 5832291 (1998-11-01), Rosen et al.
patent: 5903771 (1999-05-01), Sgro et al.
Amdhal Corporation
Chang Jung-won
Lovejoy David E.
Maung Zarni
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