CMOS integrated circuit

Details CMOS integrated circuit CMOS integrated circuit

1998-10-19

2001-10-02

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting input voltage to output current or vice versa

C327S112000, C327S538000

Reexamination Certificate

active

06297672

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an integrated circuit (IC) having a multiplicity of CMOSs (Complementary Metal-Oxide Semiconductors) formed therein, and more particularly, to an improvement in a signal transmission path or line in a ULSI (Ultra-Large Scale Integrated circuit) Of CMOs.
BACKGROUND ART
As is well known, semiconductor elements, logical circuits and the like formed as an LSI (Large Scale Integrated Circuit) are electrically connected in a predetermined manner by wiring. Likewise, in a ULSI having a multiplicity of CMOSs formed therein, CMOSs, logical circuits of CMOSs, and the like are electrically connected in a predetermined manner by wiring. Such wiring may be often formed by conductive paths or conductors of a predetermined pattern formed, for example, on the surface of an integrated circuit.
FIG. 6
shows an internal circuit of a conventional ULSI of CMOSs. In this example, there is shown a case in which a gate
11
of one CMOS at a transmitting side (hereinafter, referred to as transmitting gate) and a gate
18
of one CMOS at a receiving side (hereinafter, referred to as receiving gate) are electrically connected through a signal transmission path which is conductive path or conductor
15
in this example. Both of the transmitting gate
11
and the receiving gate
18
are constituted, in this example, by CMOS inverters (each inverter is constituted by a CMOS), respectively.
The transmitting gate
11
comprises a p-channel MOS.FET (MOS Field Effect Transistor)
12
and a n-channel MOS.FET
13
in which both gates thereof are connected with each other and connected to an input terminal
14
, both drains thereof are connected with each other and connected to one end (input end) of the conductive path
15
, source of the p-channel MOS.FET
12
is connected to a power supply terminal
16
of +VDD (a positive voltage), and source of the n-channel MOS.FET
13
is connected to a power supply terminal
17
of −VSS (a negative voltage). Source of the n-channel MOS.FET
13
may be connected to a common electric potential point or ground potential point.
On the other hand, the receiving gate
18
comprises a p-channel MOS.FET
21
and a n-channel MOS.FET
22
in which both gates thereof are connected with each other and connected to an input terminal
23
, both drains thereof are connected with each other and connected to an output terminal (not shown), source of the p-channel MOS.FET
21
is connected to the power supply terminal
16
of +VDD, and source of the n-channel MOS.FET
22
is connected to the power supply terminal
17
of −VSS. The other end (output end) of the conductive path
15
is connected to the input terminal
23
.
In such circuit configuration, since there inevitably exist a distributed capacitance CL (shown by broken line) of the conductive path
15
and an input capacitance CG (also shown by broken line) of the receiving gate
18
, when a signal is transmitted from the transmitting gate
11
to the receiving gate
18
through the conductive path
15
, the distributed capacitance CL of the conductive path
15
and the input capacitance CG of the receiving gate
18
will be charged by this signal. Assuming that an equivalent output resistance of the transmitting gate
11
is R
0
, the transition time in waveform of a voltage inputted to the receiving gate
18
is equal to R
0
×(CL+CG).
In reality, the transition time is also affected by a distributed resistance of the conductive path
15
, but usually the equivalent output resistance R
0
is dominative over this distributed resistance and hence the influence of the distributed resistance is omitted herein. In addition, the equivalent output resistance R
0
has a nature of non-linearity so that the resistance value can be varied with change of the voltage. However, for clarity of the explanation, such characteristic is ignored herein. Recently, ICs are growing in density of integration and degree of scale thereof higher and larger, and the size of an IC chip is also increasing more and more. For example, as shown in
FIG. 7
, there is not rare a ULSI in which the length of one side of its chip
24
is longer than 15 mm. In such large IC chip, wiring or conductive paths connecting circuits, elements, and the like formed in the IC chip with one another become long in their lengths, and there appears a conductive path which is longer than 20 mm. In an estimation of some ULSI, the number of conductive paths larger than 20 mm has become more than 5% of the total number of conductive paths.
FIG. 7
shows an example of the internal circuits of a conventional ULSI of CMOSs. It diagrammatically illustrates a multiplicity of gates, and wiring connecting therebetween, namely, conductive paths
25
,
26
and
27
. As shown, in addition to the conductive path
25
having a comparatively short length (200 &mgr;m or so), there are the conductive path
26
being a very long (larger than 20 mm) and the conductive path
27
which is a very long (larger than 20 mm) and has a plurality of gates as its loads. Such conductive path
27
is used in distributing a clock signal or transmitting a bus signal, and these signals affect the whole performance (operation speed or rate) of the IC chip, namely, ULSI.
In
FIG. 7
, in case that a step waveform is transmitted from transmitting gates (three gates at left side in the drawing) to corresponding receiving gates through the respective conductive paths
25
,
26
and
27
, the input waveforms at the receiving gates are as shown in
FIG. 8A
by curves
25
a,
26
a
and
27
a,
respectively, and in case that an impulse is transmitted from the transmitting gates to the corresponding receiving gates through the respective conductive paths
25
,
26
and
27
, the input waveforms at the receiving gates are as shown in
FIG. 8B
by curves
25
b,
26
b
and
27
b,
respectively. As is apparent from these waveforms, owing to that the longer conductive paths
26
and
27
have very long transition times respectively as compared with the short conductive path
25
, the propagation delay-times of the conductive paths
26
and
27
are remarkably long in respect to the step response thereof and in respect to the pulse response thereof, if the pulse width is short, the pulse is disappeared. As a result, a clock signal having a high frequency (a short repetitive period) cannot pass through a conductive path of long distance. In other words, there is an important drawback that the performance (operation speed or rate) of the whole IC chip cannot be made high.
In addition, in order to increase the density of integration of an IC and to reduce the power consumption of an IC more and more, miniaturization of a CMOS is growing and the operation speed of an unity gate is improved. However, the equivalent output resistance R
0
becomes high and the distributed capacitance of wiring per unit length tends to rather increase than is unchanged. Consequently, the transition time is further long, resulting in a shortcoming that the operation speed of the IC chip is limited more and more.
In view of such disadvantages, recently, in order to improve the throughput of wiring in an IC chip, a method of transmitting a signal in an IC chip using light has been researched or studied. However, it is necessary that light emitting elements and light receiving elements of compound semiconductors are formed on the surface of a silicon (Si) chip and that an optical waveguide is constituted separately of an electrical wiring layer. Therefore, it is difficult at present to implement such optical signal transmission method, and even if such method should be implemented, vast increases in size and cost are estimated.
DISCLOSURE OF THE INVENTION
An object of the present invention is to provide a large scale integrated circuit of CMOS structure in which a signal can be transmitted therein at high speed or rate.
In the present invention, in order to attain the above object, there is provided an integrated circuit of CMOS structure which is characterized in that a current-inp

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