Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-06-04
2003-11-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06651200
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the boundary scan test techniques and more particularly to a clocking technique for boundary scan testing and device programming.
BACKGROUND OF THE INVENTION
Boundary Scan Test is a technique which was originally developed to assist in the testing of printed circuit boards. The boundary scan technique allows a board to be tested without requiring the installation of test pads for conducting the testing.
The Boundary Scan Test protocol was formalized under IEEE Standard 1149.1 in 1990. Since the adoption of the IEEE Std. 1149.1, the Boundary Scan Test technique has proliferated electronics manufacturing and the application of boundary scan techniques has expanded beyond mere interconnect testing for printed circuit boards. Today, boundary scan is being used for microprocessor bus-emulation, In-System Programming (ISP) of custom programmable logic devices (CPLD's) and Flash memory devices, functional testing of ASIC's, and non-scannable device clusters.
Typically boundary scan testing requires long test vectors. Since the boundary scan technique is highly serial and sequential, this results in increased test execution times. The ability of the controller to shift data through the scan chain at high frequencies depends on the delay caused by buffers and drivers and the distance between the target device and scan controller. This means that the longer the path delay, the slower the TCK clock rate. In the prior art systems, operation at reasonable TCK clock rates (5-10 MHz) has been achieved by keeping the distance to within 2-3 inches (5-8 cms) and eliminating any buffering. In some cases, the use of special pods has been required. Since boundary scan systems are often used in manufacturing environments, constraining the distance and/or using special pods is usually impractical.
In view of these deficiencies with prior art boundary scan systems, there remains a need for a boundary scan technique which does not suffer from these shortcomings.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a boundary scan method and system which includes adaptive clocking techniques that compensate for path delays. The adaptive clocking techniques are suitable for both test applications and In-System Programming applications.
Advantageously, the adaptive clocking techniques according to the present invention allow a boundary scan test bus controller to operate at the maximum TCK clock rate supported by target devices. Since the effect of path delay is eliminated by the bus controller, it is no longer necessary to keep the programming system close to the target device or mandate the use of special pods.
In addition, the adaptive clocking techniques according to the present invention eliminate the principle cause of instability in testing and programming of ISP's.
In a first aspect, the present invention provides a boundary scan controller for scanning a target device, said boundary scan controller comprising: (a) a clock generator for generating a system clock; (b) a transmit module including, (i) a transmit clock generator for generating a transmit clock, said transmit clock being derived from said system clock; (ii) an output data register for storing an output data stream, said output data register having an output coupled to the target device and including means responsive to said transmit clock for shifting said output data stream to the target device; (c) a receive module having, (i) a receive clock generator for generating a receive clock, said receive clock being derived from said system clock and including a delay counter for delaying the running of said receive clock so that said receive clock starts running after said transmit clock; (ii) an input data register for storing data, said input data register having an input coupled to the target device and including means responsive to said receive clock for shifting in an incoming stream of data from the target device; (d) a state machine controller for controlling the operation of said transmit module and said receive module for performing a boundary scan of the target device.
In another aspect, the present invention provides a method for performing a boundary scan on a target device, said method comprising the steps of: (a) generating an output clock for outputting data to the target device; (b) shifting a serial stream of output data on said output clock to said target device; (c) generating an input clock after a predetermined delay for receiving a serial stream of incoming data from the target device; (d) wherein said predetermined delay provides a period of time for the target device to respond to said serial stream of output data.
REFERENCES:
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5706297 (1998-01-01), Jeppesen, III et al.
patent: 6091261 (2000-07-01), De Lange
patent: 6286118 (2001-09-01), Churchill et al.
patent: 6327684 (2001-12-01), Nadeau-Dostie et al.
Barahmand Mehrdad
Taheri Saeed
Acculogic, Inc.
De'cady Albert
Dooley Matthew
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