Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-09-13
2005-09-13
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S005110, C714S710000, C711S113000, C711S114000
Reexamination Certificate
active
06944807
ABSTRACT:
The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.
REFERENCES:
patent: 6141779 (2000-10-01), Hill et al.
Hill J. Michael
Howlett Warren K
Lachman Jonathan E.
Hewlett-Packard Development Company LP.
Lamarre Guy
Pessetto John
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