Method and apparatus for ABIST diagnostics

Details Method and apparatus for ABIST diagnostics Method and apparatus for ABIST diagnostics

2006-07-11

2006-07-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07076706

ABSTRACT:
A method for real time capture of the desired failing chip cell diagnostic information from high speed testing of a semiconductor chip with on chip LSSD registers having built in self test functions and a fail trap register, and there is provided a programmable skip fail counter, and a hold and compare function circuit. The programmable skip counter is enabled for initialization to a “record first fail” mode, and then with non-zero values of the skip counter to a “record next fail” mode with scan initialization of the LSSD registers of the semiconductor chip. The diagnostic information for the chip is obtained by collecting data from scanning the circuits of said semiconductor chip for a failing cell for immediate scan-out off-chip at a level of assembly test.

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