Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-06-12
2007-06-12
Smith, Bradley K. (Department: 2891)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257SE21546
Reexamination Certificate
active
11021269
ABSTRACT:
A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
REFERENCES:
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6136654 (2000-10-01), Kraft et al.
patent: 6174775 (2001-01-01), Liaw
patent: 6297103 (2001-10-01), Ahn et al.
patent: 6352885 (2002-03-01), Wieczorek et al.
patent: 6479403 (2002-11-01), Tsei et al.
patent: 6566205 (2003-05-01), Yu et al.
patent: 6596599 (2003-07-01), Guo
patent: 6614067 (2003-09-01), Liaw
patent: 6632714 (2003-10-01), Yoshikawa
patent: 6706581 (2004-03-01), Hou et al.
patent: 6716695 (2004-04-01), Hattangady et al.
patent: 6720221 (2004-04-01), Ahn et al.
patent: 6746900 (2004-06-01), Liu et al.
patent: 2004/0026687 (2004-02-01), Grupp et al.
patent: 2004/0142524 (2004-07-01), Grupp et al.
patent: 2004/0164318 (2004-08-01), Lee et al.
patent: 2005/0269650 (2005-12-01), Pidin
Sekine, et al., “Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent Interface Property and Ultra-low Leakage Current,” IEEE, 2003, pp. 103-106.
Iwamoto, et al., “A Highly Manufacturable Low Power and High Speed HfSiO CMOS FET with Dual Poly-Si Gate Electrodes,” IEEE, 2003, pp. 1-4.
Shi, et al., “Mobility Enhancement in Surface Channel SiGe PMOSFETs With HfO2Gate Dielectrics,” IEEE Electron Device Letters, vol. 24, No. 1, Jan. 2003, pp. 34-36.
Tamura, et al., “SiN-capped HfSiON Gate Stacks with Improved Bias Temperature Instabilities for 65 nm-node Low-Standby-Power Transistors,” 2004 Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 210-211.
Hu, C., “Device Challenges and Opportunities,” 2004 Symposium on VLSI Technology, Digest of Technical Papers, IEEE, pp. 4-5.
Fung, et al., “65nm CMOS High Speed, General Purporse and Low Power Transistor Technology for High Volume Foundry Application,” 2004 Symposium on VLSI Technology, Digest of Technical Papers, IEEE, pp. 92-93.
Yang, et al., “Effect of polycrystalline-silicon gate types on the opposite flatband voltage shift in n-type and p-type metal-oxide-semiconductor field-effect transistors for high-k-HfO2dielectric,” Applied Physics Letters, vol. 83, No. 3, Jul. 14, 2003, American Institute of Physics, pp. 308-310.
Diaz, C.H., “Bulk CMOS Technology for SOC,” Extended Abstracts of Internatinal Workshop on Junction Technology 2002, Japan Society of Applied Physics, pp. 91-96.
Ma, T.P., “Making Silicon Nitride Film a Viable Gate Dielectric,” IEEE Transactions of Electron Devices, vol. 45, No. 3, Mar. 1998, pp. 680-690.
Shiraishi, et al., “Physics in Fermi Level Pinning at the PolySi/Hf-based High-k Oxide Interface,” 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 108-109.
Cartier, et al., “Systematic study of pFET Vtwith Hf-based gate stacks with poly-Si and FUSI gates,” 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 44-45.
Shima, M., “<100> Strained-SiGe-Channel p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance,” Jun. 2003, Fujitsu Sci. Tech. J., vol. 39, 1, pp. 78-83.
Fernandez, et al., “Properties of Si3N4/SixGe1-xMetal-Insulator-Semiconductor Capacitors,” Electronics Letters, Sep. 26, 1991, vol. 27, No., 20, pp. 1826-1827.
Yeo, et al., “Enhanced Performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Geranium,” IEDM 2000, pp. 753-756.
Lu, et al., “p-Type SiGe Transistors with Low Gate Leakage Using SiN Gate Dielectric,” IEEE Electron Device Letters, vol. 20, No. 10, Oct. 1999, pp. 514-516.
She, et al., “JVD Silicon Nitride as Tunnel Dielectric in p-Channel Flash Memory,” IEEE Electron Device Letters, vol. 23, No. 2, Feb. 2002, pp. 91-93.
Khare, et al., “Highly Robust Ultra-Thin Dielectric for Giga Scale Technology,” 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 218-219.
Wang, et al., “High-Quality MNS Capacitors Prepared by Jet Vapor Deposition at Room Temperature,” IEEE Electron Device Letters, vol. 13, No. 9, Sep. 1992, pp. 482-484.
Weber, et al., 55 nm high mobility SiGe(:C) pMOSFETs with HfO2gate dielectric and TiN metal gate for advanced CMOS, 2004 Symposium on VLSI Technology, Digest of Technical Papers, IEEE 2004, pp. 42-43.
Tseng, et al., “Ultra-Thin Decoupled Plasma Nitridation (DPN) Oxynitride Gate Dielectric for 80-nm Advanced Technology,” IEEE Electron Device Letters, vol. 23, No. 12, Dec. 2002, pp. 704-706.
Tseng, et al., “Threshold Voltage Instability and Plasma Induced Damage of PolySi/HfO2 Devices—Positive Impact of Deuterium Incorporation,” 2004 IEEE International Conference on Integrated Circuit Design and Technology, pp. 255-259.
Chen Shang-Chih
Tsai Ching-Wei
Wang Chih-Hao
Slater & Matsil L.L.P.
Smith Bradley K.
Taiwan Semiconductor Manufacturing Company , Ltd.
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