Method and apparatus for a scannable hybrid flip flop

Details Method and apparatus for a scannable hybrid flip flop Method and apparatus for a scannable hybrid flip flop

2000-04-28

2003-09-30

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C327S144000

Reexamination Certificate

active

06629276

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to radiation hardened integrated circuits and, more particularly, to scannable latches for radiation hardened integrated circuits.
2. Background Description
Increasingly, space-based communication systems are including Integrated Circuits (IC) made in advanced deep sub-micron Field Effect Transistor (FET) technology. Typically, these ICs are in the insulated gate silicon technology commonly referred to as complementary metal oxide semiconductor (CMOS). CMOS ICs are advantageous in that they operate at high speed and use low power, as compared to what other technologies require for comparable speed and function.
In a space-based environment, however, ionic strikes by sub-atomic cosmic particles are known to introduce circuit disturbances. These disturbances are known as Single Event Effects (SEEs) and, as Single Event Upsets (SEUs) when occurring in storage elements. Radiation hardened storage elements latches are well known and are used, effectively, to reduce or eliminate SEE in space based IC registers, latches and other storage elements. These radiation hardened storage elements can be referred to as radiation hardened latches and are designed to protect from disturbance what is stored in them in spite of any cosmic particle hits that the storage elements might sustain.
In the past, level sensitive scan design (LSSD) latches were used in spaced-based applications to reduce an integrated circuit's SEE sensitivity.
FIG. 1
is a block diagram of a conventional LSSD latch
100
. The LSSD latch
100
includes a first stage
102
and a second stage
104
. The first stage
102
includes a serial input SCANIN (SI)
106
clocked by a clock A
0
signal
108
and a data input DATAIN (DI)
110
clocked by a clock C
0
signal
112
. An output
114
of the first stage
102
is the input of the second stage
104
which is clocked by a clock B
0
signal
116
. An output DATAOUT
118
of the second stage
104
is an output P
10
of the LSSD latch
100
.
Typically, LSSD latches
100
are linked together serially to form several scan chains on a chip by connecting the output DATAOUT
118
of one LSSD latch
100
(in addition to its normal logic path connection) to the SCANIN input
106
of the next LSSD latch
100
in the chain. The IC logic is designed such that logic functions are bounded by scan chains. Thus, test data may be scanned in on one scan chain, at the input to the particular logic function and the logic function's response to the test data may be scanned out on another chain at the logic function's output. The data scanned out may be compared against an expected result and analyzed to determine if and where logic errors exist in the function.
During normal operation, the C
0
and B
0
clock signals
112
and
116
are non-overlapping phases derived from the same system clock. During each clock cycle, data at data input DATAIN
110
is latched in the first stage
102
when the C
0
clock signal
112
is driven high. Then, after the first stage latch
102
has set, the C
0
clock signal
112
is driven low. Next, the B
0
clock signal
116
is driven high, passing the contents of the first stage
102
to the second stage
104
. As the second stage is setting, the stored data passes out of the second stage on output P
10
DATAOUT
118
and the second stage is set when the B
0
clock signal
116
is driven low. The next clock cycle begins when the C
0
clock signal
112
is again driven high.
During testing, initially, the C
0
clock signal
112
is held low for all latches
100
. Data is scanned in serially on the scan input SCANIN
106
by driving the A
0
clock signal
108
(for one or more scan chains) with the B
0
clock signal
116
until the entire test pattern has been scanned into the chain. Typically, test data is loaded into all of the scan chains, either individually or, several at a time. Once the test pattern has been scanned into each selected input test chain and the stored test pattern data has had time to pass through the function, the C
0
clock signal
112
is pulsed with a single pulse to clock the function output into first stage
102
of all of the LSSD latches
100
. The single pulse of C
0
clock signal
112
is followed by a pulse on the B
0
clock signal
116
to pass the function results to the second stage
104
of the LSSD latches. Then, the results are scanned out of the scan chains, driving individual scan chain A
0
clock signal
108
with the B
0
clock signal
116
. Thus, individual logic functions can be tested, extensively, providing a high degree of functional certainty.
Unfortunately, modern electronic computer automated design (ECAD) tools, which are directed more to automated test pattern generation (ATPG), are incompatible with LSSD. These modern ECAD tools are incapable of using the multiple clock signals (A
0
, B
0
and C
0
)
108
,
116
, and
112
that LSSD latches
100
require. Instead, these modem ECAD tools are adapted for logic circuits implemented using edge-triggered latches.
Edge-triggered latches set on the falling or rising edge of a single clock. For example,
FIG. 2
illustrates a conventional scan d-flip-flop (scan dff)
200
. The scan d flip-flop
200
includes a 2:1 multiplexer
202
, which is coupled to a first level sensitive latch
204
. The first level sensitive latch
204
is coupled to a second level sensitive latch
206
. The scan dff
200
is clocked by a clock signal
207
. The clock signal
207
is split into complementary signals by inverting clock signal
207
with inverter
208
. The complementary clock signals are provided to first level sensitive latch
204
and second level sensitive latch
206
, gating first and second pairs of pass gates
210
,
212
and
214
,
216
, respectively.
When selected by select signal
218
, the DATAIN
210
input passes through the 2:1 multiplexer
202
to the first pair of pass gates
210
,
212
as complementary outputs
220
,
222
. When the clock signal
207
is low, pass gates
210
,
212
, are turned on so that data on complementary outputs
220
,
222
are passed to first level sensitive latch
204
and, tentatively, are stored therein. With the clock signal
207
low, the second pair of pass gates
214
,
216
are contemporaneously turned off, and isolate the second level sensitive latch
206
from the outputs
224
,
226
of the first level sensitive latch
204
.
The rising edge of clock signal
207
turns on the second pair of pass gates
214
,
216
as the output of inverter
208
falls, simultaneously, to turn off the first pair of pass gates
210
,
212
. When the first pair of pass gates
210
,
212
are turned off, the complementary outputs
220
,
222
are isolated from the first level sensitive latch
204
and, so, data is latched in the first level sensitive latch
204
. When the second pair of pass gates
214
,
216
are turned on, outputs
224
,
226
of the first level sensitive latch
204
are passed to the second-level sensitive latch
206
. The state of outputs
224
,
226
is stored, tentatively, in the second level sensitive latch
206
and, simultaneously, is passed out on an output DATAOUT
118
. When clock signal
207
falls, on the next clock cycle, the second pair of pass gates
214
,
216
are turned off, isolating the second level sensitive latch
206
from the first level sensitive latch
204
, latching data in the second level sensitive latch
206
to complete the clock cycle.
Normally, when the clock signal
207
is well behaved with regularly spaced high and low periods, it is sufficient that data provided to the input DATAIN
110
meet setup (i.e., be valid for a specified period prior to the rise of clock signal
207
) and hold (i.e., remain valid for a specified period after the rise of clock signal
207
) timing requirements. At any other time, other than when clock signal
207
is rising, the state of DATAIN input signal
110
is specified as a “don't care” condition.
Unfortunately, an upsetting event occurring in the clock tree

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