Static information storage and retrieval – Systems using particular element – Ternary
Reexamination Certificate
1999-12-10
2001-01-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ternary
Reexamination Certificate
active
06181596
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to electronic circuits implementing RAM functionality.
2. Description of the Related Art
The active memory of modem computer systems relies heavily on the use of RAMs to perform active, volatile storage of both data and instructions. Static and dynamic RAMs are well known and well studied in the art. Dynamic memory is the workhorse of the main memory array of most modern computer systems, while static memory is generally used in high-speed memory caches, local to the primary processor.
The typical SRAM is composed of a large number of memory cells, each memory cell having a unique address within the memory. SRAM cells have typically been coupled to a pair of bit lines via a pair of word line transistors. When the word line signal has received a logical high signal assertion, data is exchanged between a pair of nodes internal to the SRAM cell and the pair of bit lines. The word line signal has generally been generated as a logical function of various bits of a received address. Depending on whether the operation is a read or a write, data is either transferred from the internal nodes of the RAM cell to the bit lines, or from the bit lines to the internal nodes of the RAM cell.
Sense amplifiers have typically been employed to increase the speed with which the bit line logic state changes (i.e., changes, in either voltages or currents, that represent transactions between logic states on the bit lines can be detected during reads). A sense amplifier has typically been constructed to detect small differences (i.e., the differential) in voltage or current between the bit lines of the bit line pair. The sense amplifier has typically contained a static CMOS transistor pair for each bit line with positive feedback. It drives the bit line with the higher logic state voltage to the positive rail and the bit line with the lower logic state to the negative rail.
However, even before input data arrives at the sense amplifier, small fluctuations between the bit lines may be detected. The fluctuations in the bit line may result from any of a variety of factors, including crosstalk from other memory cells and bit lines, electrical or switching noise, or other environmental factors. These fluctuations are overcome by the differential intentionally placed on the bit lines once the inputs arrive, but premature reading of the bit lines may inadvertently cause an erroneous measurement.
To reduce the chance of such an erroneous, premature reading, a delay circuit has typically been employed to delay the operation of the sense amplifier until the SRAM cell being read has had sufficient time to produce differential on the bit lines. The delay, typically originating from a clock edge, delays the triggering of the sense amplifier until the difference between the bit lines may be assumed to be caused by actual data from the RAM cell. The delay has sometimes been determined in a worse case scenario, i.e., to provide as much assurance as possible that the sense amplifier will not trigger early and thereby produce a false result. However, high performance SRAMs may incorporate some type of self-timing.
SUMMARY OF THE INVENTION
The present invention provides an improved RAM circuit through the use of N-NARY logic gates. The RAM circuit includes two columns of RAM cells, two pairs of bit lines, an N-NARY input logic circuit, a SENSE signal generation circuit (also referred to as a sense amplifier trigger circuit), two sense amplifiers, and an output driver circuit. One portion of the RAM circuit includes one of the columns of RAM cells, one of the pairs of bit lines, and one of the sense amplifiers. A second portion of the RAM circuit includes the second column of RAM cells, the second of the pairs of bit lines, and the second sense amplifier. Each of the RAM cells may be a six-transistor RAM cell, and together with a corresponding RAM cell in the other column forms a RAM cell pair that is driven by a common word line signal. Each RAM cell pair bridges both columns of RAM cells. Each column of RAM cells has a corresponding pair of bit lines, and each individual RAM cell is coupled to the bit lines by a word line circuit. Although each of the two RAM cells in a RAM cell pair are individually connected to distinct bit line pairs, the connection is accomplished concurrently by a common word line signal. When the word line signal is asserted for any one RAM cell pair, then no other word line signal is simultaneously asserted for any other RAM cell pair.
The word line signal for each of the RAM cell pairs is driven by an N-NARY address gate (or group of N-NARY address gates) that selectively asserts word line signals as a function of an address signal. The address gate is quite simple, quite small, and quite fast as compared to other word line signal drivers. The received address signal may be an N-NARY signal, or may be a collection of N-NARY signals. The output of the N-NARY address gate (or collection of N-NARY address gates) has a distinct output wire for each row of RAM cells in the RAM circuit, each row having one RAM cell in each of several columns, and responds to the address by providing a 1-of-N (N-NARY) output signal over the output wires. Each of the wires of the 1-of-N output signal from the N-NARY address gate is therefore connected to a distinct RAM cell pair, and only one word line signal may be asserted at any given time.
The N-NARY address is also provided to a SENSE signal generation circuit that performs a logical (Boolean) OR upon the N-NARY signal within the address signal. If there are multiple N-NARY address signals, the results of ORing each N-NARY signal are further ANDed. The SENSE signal generation circuit provides a sense amplifier trigger signal whose delay is a function of the latest arriving input address, rather than a direct function of clock timing. The SENSE signal generation circuit, therefore, corrects itself for any delays in the arrival of the address signal with respect to the clock timing. Moreover, delays do not have to be based on a “worst case” scenario of maximum tardiness in the arrival of the address, allowing the RAM circuits to take full advantage of early address arrival. Providing a logical AND-OR of these possible input addresses ensures that the sense amplifier trigger signal is not asserted until the required addresses are available for word line generation. According to a second aspect of the present invention (useful only in circuits having a very few word lines), rather than relying on address signals for the logical OR, the word line signals themselves are used in a logical OR for triggering the SENSE signal generation circuit. The sense signal may be further delayed from the address arrival time by delays that reflect the bit line evaluation time, so that the sense signal timing is more closely matched to the bit line evaluation time.
Finally, the present invention also includes an output circuit that provides both true and complemented values of output data without the need for any latches. Thus, the output drives subsequent N-NARY logic signals without the need for conversion. However, if a different signal width is desired, such as a signal width of 1 of 4 rather than a signal width of 1 of 2, then the two bit line pairs may be combined in a very simple output circuit. Moreover, the output circuit may be implemented by incorporation into the subsequent N-NARY logic gate directly without the need for signal width conversion or latching.
Additionally, according to one aspect of the present invention, the N-NARY RAM circuit provides both bit lines of each RAM cell column (that is, of each sense amplifier) to an output driver. In the vocabulary of N-NARY signals, each sense amplifier provides a 1-of-2 signal rather than merely a single bit line to the subsequent device. Bit line pairs may themselves be paired into groups of four bit lines, and easily converted to a 1 of 4 or other N-NARY output signal protocols. According to on
Blomgren James S.
Horne Stephen C.
Seningen Michael R.
Booth Matthew J
Booth & Wright, L.L.P.
Intrinsity, Inc.
Phan Trong
Wright Karen S.
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