Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1998-02-05
2000-05-23
Tokar, Michael
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 95, 326 98, 326112, H03K 19096, H03K 1920
Patent
active
060669659
ABSTRACT:
The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.
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Blomgren James S.
Horne Stephen C.
Petro Anthony M.
Potter Terence M.
Seningen Michael R.
Booth Matthew J.
Cho James H.
EVSX, Inc.
Tokar Michael
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