Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-29
2003-09-23
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S588000, C438S593000, C438S595000, C438S286000
Reexamination Certificate
active
06624024
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor manufacture and, more particularly, to a method and structure for a source local interconnect for a flash memory device.
BACKGROUND OF THE INVENTION
Floating gate memory devices such as flash memories include an array of electrically-programmable and electrically-erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor including a floating gate interposed between a control (input) gate and a channel. A layer of high-quality tunnel oxide used as gate oxide separates the transistor channel and the floating gate, and an oxide-nitride-oxide (ONO) dielectric stack separates the floating gate from the control gate. The ONO stack typically comprises a layer of silicon nitride (Si
3
N
4
) interposed between underlying and overlying layers of silicon dioxide (SiO
2
). The underlying layer of SiO
2
is typically grown on the first doped polycrystalline silicon (polysilicon) layer. The nitride layer is deposited over the underlying oxide layer, and the overlying oxide layer can be either grown or deposited on the nitride layer. The ONO layer maximizes the capacitive coupling between the floating gate and the control gate and minimizes the leakage of current.
To program a flash cell, the drain region and the control gate are raised to predetermined potentials above a potential applied to the source region. For example 12, volts are applied to the control gate, 0.0 volts are applied to the source, and 6.0 volts are applied to the drain. These voltages produce “hot electrons” which are accelerated from the substrate across the gate oxide layer to the floating gate. Various schemes are used to erase a flash cell. For example, a high positive potential such as 12 volts is applied to the source region, the control gate is grounded, and the drain is allowed to float. More common erase bias' conditions include: a “negative gate erase” in which −10V is applied to the control gate (V
g
), 6V is applied to the source (V
s
), a potential of 0V is applied to the body (V
body
), and the drain is allowed to float (V
d
); and a “channel erase” which comprises a V
g
of −9V, a V
body
of 9V, and a V
s
and V
d
of 9V or floating. In each case these voltages are applied for a timed period, and the longer the period the more the cell becomes erased. A strong electric field develops between the floating gate and the source region, and negative charge is extracted from the floating gate across the tunnel oxide to the source region, for example by Fowler-Nordheim tunneling.
In a flash memory device, the sources associated with each transistor within a sector are tied together, typically through the use of conductive doping of the wafer to connect the sources of each transistor within a column. The columns within the sector are tied together using conductive plugs and a conductive line.
FIG. 1
depicts a cross section of a transistor and other structures of a conventional flash electrically-erasable programmable read-only memory (E
2
PROM) device.
FIG. 1
depicts the following structures: semiconductor substrate assembly comprising a semiconductor wafer
10
, transistor source
12
and drain
14
diffusion regions within semiconductor wafer
10
, gate (tunnel) oxide
16
, floating gates
18
typically comprising a first polysilicon layer, capacitor dielectric
20
typically comprising an oxide-nitride-oxide (ONO) stack, control gate (word line)
22
typically comprising a second polysilicon layer, a transistor stack capping layer
24
typically comprising silicon nitride (Si
3
N
4
) or tetraethyl orthosilicate (TEOS), oxide or nitride spacers
26
, a planar dielectric layer
28
such as borophosphosilicate glass (BPSG), digit line plugs
30
connected to drain regions
14
, and a conductive line
32
typically comprising aluminum which electrically couples each plug
30
within a row of transistors.
A goal of design engineers is to increase the density of the transistors to enable a decrease in the size of the semiconductor device. One way this can be accomplished is to decrease the size of the transistors. As a semiconductor die typically comprises transistors numbering in the millions, even a small decrease in the transistor size can result in a marked improvement in device density. One obstacle to decreasing the transistor size is that if the cross-sectional area of the source region
12
becomes too small the electrical resistance of the source diffusion region increases beyond a desirable level and the device may become unreliable. The undesirable increase in resistance is exacerbated by the relatively extreme length of the diffusion region which functions as a source region for all transistors within a column. Thus, to minimize the resistance the source region must be heavily doped with conductive atoms. One problem with providing a heavily doped source region is that the dopants tend to diffuse away from the source region, especially with high-temperature processing of subsequent manufacturing steps. The dopants can migrate into the channel region of the device thereby effectively decreasing the channel length interposed between the source and drain regions underneath the transistor stack. This decrease in channel length can produce problems known as “short channel effects” such as a transistor with a lowered threshold voltage, which itself can produce an unreliable device.
One method for allowing a decrease in transistor size by decreasing the source length which avoids short channel effects is to provide a source local interconnect (LI)
34
as depicted in
FIG. 2. A
source LI can comprise the use of a conductive interconnect which electrically couples each source in one column of transistors of a flash device with all other sources. The interconnect is typically formed from a single layer of patterned, conductively-doped polysilicon, a metal such as tungsten, or another conductive material lying between two adjacent columns of transistors. An LI of polysilicon and a method for forming the LI has been proposed by R. Lee in U.S. Pat. Nos. 5,149,665 and 5,270,240, each of which is assigned to Micron Technology, Inc. and incorporated herein by reference as if set forth in their entirety.
One concern with source local interconnects is to maintain an adequate isolation between the interconnect and the word lines (control gates) of each adjacent transistor to prevent shorting and to sustain the maximum voltage between the source and control gate of the flash device. For example, in program (write) mode, 12 volts can be applied to the control gate while 0 volts is applied to the source. While maintaining isolation is necessary, an attempt is made to keep the spacing between the LI and the word lines to a minimum so that the transistors, and thus the memory array, can be made as small as possible.
A method for forming a local interconnect for a semiconductor device, and an inventive structure resulting from the method, which reduces or eliminates the problems described above would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method for forming a semiconductor device, and an inventive semiconductor device resulting from the method, which, among other advantages, allows for a more scaleable device than is found with flash memory devices having diffused sources. The inventive method and device further allows for minimal spacing between a local interconnect and adjacent transistor features.
In accordance with one embodiment of the invention a plurality of transistor stacks each having an associated source and drain region, a nitride capping layer, and nitride spacers formed along each stack is provided. During the etch of the transistor stacks the gate oxide is typically not completely removed from the source and drain regions and remains until later processing steps and protects the silicon wafer in the source/drain areas. A thin blanket nitride barrier layer is then formed over exposed surfaces. Next, a planarized blanke
Chen Chun
Prall Kirk D.
Booth Richard
Martin Kevin D.
LandOfFree
Method and apparatus for a flash memory device comprising a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for a flash memory device comprising a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for a flash memory device comprising a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3051621