Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer
Reexamination Certificate
2000-01-12
2004-02-03
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Concurrent input/output processing and data transfer
C710S021000, C710S029000, C714S720000
Reexamination Certificate
active
06687766
ABSTRACT:
FIELD OF INVENTION
This invention relates to concept of transferring information in a computer program product for use with a computer system having a main storage device in processing communication with a plurality of input/output devices.
BACKGROUND OF THE INVENTION
In a network computing environment, multitudes of commands and requests for retrieval and storage of data are processed every second. To properly address the complexity of routing these commands and requests, a number of different resolutions have been implemented. In some data processing architectures, such as International Business Machines Enterprise System Architecture/390 (Enterprise System Architecture/390 is a registered trademark of International Business Machines Corporation), a channel subsystem is utilized to pass information between the main storage and input/output (I/O) devices. The channel subsystem includes one or more channel paths, each including one or more channels and one or more control units. Recently developed technologies such as the International Business Machines ESCON switch (ESCON is a registered trademark of International Business Machines Corporation), connect the I/O devices to the main memory through the control units using legacy channels to support the data transfer there between.
But as the technology improves, the performance of new system processors will require many more legacy channels than are presently in use to support the resulting increase of information transfer in the data processing systems. Current architectural constraints make the addition of such legacy channels an expensive proposition. A further challenge is to provide the link data rate required to support the data rates of new I/O devices such as DASDs and Tapes. In this case, simply adding more legacy channels does not adequately address the problem. A new architecture is needed that can scale up to the higher link speeds needed for normal transaction processing. Therefore, any new proposed architecture, must include a capacity to accommodate higher bandwidth channel links such as Fibre Channel links while providing better data rates and higher link speeds.
This application is being filed at the same time as related application, Ser. Nos. 09/172,488, 09/172,696, and 09/172,462.
This application incorporates by reference the following patents and publications:
1) Fibre Channel Single Byte-2(FC-SB-2) Architecture (AR-6865-00-POK)
2) Fibre Channel (FC-PH) REV 4.3 ANSI X3.230-199x
3) U.S. Pat. No. 5,526,484 to Casper et. al.
SUMMARY OF THE INVENTION
The present invention provides for a computer program product for use with a computer system having a main storage device in processing communication with an information transfer interface mechanism capable of coupling to a plurality of input/output devices. The computer program device comprises of a data storage element included in the main storage device having a computer usable medium with computer readable program means for receiving and retrieving data and computer readable code means for concurrently receiving multiple packets of data from said interface mechanism. It also includes computer readable code means for concurrently storing multiple packets of data concurrently in said data storage element as well as computer readable code means for storage and retrieval of multiple packets of data concurrently between said interface mechanism and said data storage element. In one embodiment of the present invention the interface mechanism can include a control unit and channels and in yet another embodiment a fabric is in processing communication with the control unit and the channels. The computer product can also comprise computer readable code for transferring information using time division multiplexing. It can also comprise computer readable code for interleaving multiple starts each to a separate device on one channel by using multiplexing capability.
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Casper Daniel F.
Dugan Robert J.
Flanagan John R.
Huang Catherine C.
Ricci Louis W.
Campbell John E.
Ehrlich Marc A.
Elamin Abdelmoniem
Gaffin Jeffrey
Gonzalez Floyd A.
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