Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Metastable state prevention
Reexamination Certificate
2001-12-28
2004-02-10
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Metastable state prevention
C327S022000, C327S198000, C327S023000
Reexamination Certificate
active
06690203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to logical circuit design, and in particular the invention is directed to a failure-free synchronizer.
Portions of the disclosure of this patent document contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever.
2. Background Art
Most of today's logical circuit design is synchronous. Synchronous logical circuit design follows an assumption that all components within a system follow a global (system-wide) clock cycle. Events and interactions among various parts can be assumed to happen at discrete time cycles marked by the global clock. Having this assumption can greatly simplify circuit design. As such most of the computers and electronic equipment available today are synchronous.
One area of focus within logical circuit design is building synchronizers. A synchronizer is a circuit that samples a data input. For example, a synchronizer can be used in a computer to detect whether a user has pressed a key on the keyboard. In this case, the data input is the signal that is transmitted from the keyboard to the computer processor when a key is pressed. The synchronizer polls the system bus (a place where the computer receives signals from different components) to see whether a signal from the keyboard has arrived. The polling (sampling) is done at periodic intervals. So in essence the synchronizer is constantly asking “has a key been pressed on the keyboard at this clock cycle?” Other example uses of synchronizers include sampling data that is transferred among parts of a computer (e.g. hard drives) or among different computers across a network.
Synchronization Failure
In the context of synchronous systems that engaged in high-speed communications between independent clock domains, circuit designers found a new class of problems related to using a synchronizer to accept an unsynchronized signal into a clock domain. One of the problems is called synchronization failure. For example, synchronization failure occurs sometimes when a computer system uses a synchronizer to accept signals from external sources that do not follow its own clock cycles. Sometimes the problem occurs within a computer system, where synchronizers are used to synchronize high-speed communication among components that have disparate clock systems.
To better understand synchronization failure, consider again the hypothetical keyboard example (though in real life the keyboard may not be sending high-speed signals that would cause failure). When a user presses a key, the circuit transmits a “1” signal to the synchronizer. At every clock cycle, the computer system also sends periodic control signals of “1” to the synchronizer to notify that it is time to sample. Thus the synchronizer has to watch for two input signals. If the keyboard signal arrives in the interval between two samplings and remains “1” until the synchronizer receives the next “1” from the clock and samples again, then the synchronizer should have no problem recognizing and acknowledging this keyboard signal. If, however, the keyboard signal is withdrawn because the user has let go of the key right before the next clock signal arrives, then there is potential for synchronization failure. In the circuit the withdrawal will be represented by the keyboard signal going from “1” back to “0”, which represents no signal. Failure can also occur in the situation when a “0” switches to a “1”. Research and practical experiences have shown that the synchronizer may not be able to determine if the switch happens before or after the arrival of the control signal from the system clock. The assumptions of classical physics shows that it is impossible for any device to determine, within a bounded time period, the correct ordering of these two events—the arrival of an unsynchronized switch in input signal and the arrival of a synchronized control signal. However, the device is guaranteed to decide eventually. The state in which the synchronizer is deciding is called the metastable state. If the metastable state lasts a very long time, a failure can occur in a synchronous system. As such, designers of synchronous systems have to accept certain risk of system failure. In many instances, they are able to reduce the occurrence of such risk to an infinitesimally small number by adding latency in circuits that can slow down overall system performance.
Asynchronous Arbiter
Prior art attempts in solving the synchronization failure include using asynchronous arbiters for the purpose of synchronization. An arbiter is a device that determines whether a particular event happened before or after another. The principle behind the asynchronous arbiter is that synchronization failure may be avoided by making the sampling system completely asynchronous. In essence, if no clock demands that the sampling system make its decision after a certain, fixed amount of time, system operation can be suspended until the decision has been resolved. Atypical CMOS arbiter is shown in FIG.
1
. This is the commonly implemented R-S latch with a filtering circuit on the output. The arbiter works as follows: if it decides on a (i.e., it determines that a happened first), then output u is asserted. If the arbiter decides on b, then output v is asserted. The two inputs in this case are the unsynchronized input data and the synchronized clock (or control) signal.
In contrast to how this device is used in synchronous circuits, the asynchronous arbiter is allowed to go into a metastable state if the two inputs arrive nearly simultaneously. The filtering circuit on the output (a pass-gate-transformed pair of NOR gate/inverter hybrids) ensures that the arbiter outputs u and v do not change until the internal node voltages are separated by at least a p-transistor threshold voltage—meaning that the internal nodes have left the metastable state. At that time, the arbiter has “made up its mind” and there is no possibility of an output glitch. Although the metastable state in theory can last forever, in practice it is usually a very short period. This is the reason that asynchronous arbiters are attractive—the average delay of the arbiter is likely to be much smaller than the latency that would be required to reduce the probability of synchronization failure to acceptable levels (in a synchronous implementation).
Expressed as a Production Rule Set (PRS), a rule set that acts as the blueprint for circuit building, the simple CMOS arbiter may be written as follows:
a
⋀
t
↦
s
↓
b
⋀
s
↦
t
↓
⫬
a
⋀
⫬
t
↦
s
↑
⫬
b
⋀
⫬
s
↦
t
↑
(
1
)
A rule G
s↓ means that the variable s is set to false when the condition G is true. Rules of the form G
s↓ correspond to pull-down chains (meaning that the voltage of the signal s is being pulled down to a level representing false) and G
s ↑ correspond to pull-up chains (meaning that the voltage of the signal s is being pulled up to a level representing true). The “
” symbol represents an “and”. For example, in the first rule both a and t have to be true for s to be pulled down. The “
” symbol represents taking a negation, which is done by taking the opposite value of the variable next to “
”. So the third rule reads: “If the negation of a and the negation of t are both true then s is pulled up.” From these production rules the circuit as shown in
FIG. 1
is built. This circuit exhibits metastability when both input values a and b are true simultaneously.
A filtering circuit is introduced to prevent the outputs from changing until the arbiter has left the metastable state.
The arbiter is specified by the following handshaking expansion
*
[
[
a
→
u
↑
;
[
⫬
a
]
;
u
↓
&VerticalS
Manohar Rajit
Martin Alain J.
Nyström Mika
California Institute of Technology
Chang Daniel
Coudert Brothers LLP
Harriman II, Esq. J. D.
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