Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2005-06-28
2005-06-28
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000, C326S096000
Reexamination Certificate
active
06911846
ABSTRACT:
The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.
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Blomgren James S.
Horne Stephen C.
Petro Anthony M.
Potter Terence M.
Seningen Michael R.
Booth Matthew J.
Intrinsity, Inc.
Tran Anh Q.
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