Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2007-09-04
2007-09-04
Chambliss, Alonzo (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257SE21521, C257SE21529, C438S014000, C250S310000, C250S492230, C250S492220
Reexamination Certificate
active
10293595
ABSTRACT:
A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
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Hsueh Gary
Lymberopoulos Dimitris
Mohan Sukesh
Applied Materials Inc.
Chambliss Alonzo
McDermott & Will & Emery
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