Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-29
2002-06-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06405334
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to field programmable gate arrays (FPGAS) and, more particularly, to methods and apparatus for characterizing the AC parameters of an FPGA internal cell array.
BACKGROUND OF THE INVENTION
Gate arrays and field programmable gate arrays (FPGAs) are well known in the art. In general, a gate array is an integrated circuit that includes a plurality of predetermined transistor sizes determined by the manufacturer or vendor. Once the transistor size is set, the plurality of transistors are deposited, in layers, on a substrate to form a base or generic array. The manufacturer creates a library of logic cells by combining a plurality of transistors.
When a user identifies a specific need or functionality for a gate array, the final layer(s) are deposited over the base array, customizing the gate array in accordance with the user's needs. The individual logic cells are connected together in such way so as to achieve an output desired by the user. After the gate array is manufactured, its internal logic is set and cannot be altered.
Although the cost of the final customized layers are borne by the user, savings are realized since the manufacturing costs associated with producing the base array of transistors is spread over a large number of gate arrays.
Static random access memory (SRAM) based FPGAs are integrated circuits that are electrically programmable by the user/customer. The configuration of the FPGA may be changed from time to time to provide different outputs from the same integrated circuits when the user applies external control signals and a data stream to the FPGA. An FPGA includes a plurality of configurable elements (e.g., AND gates, NOR gates, XOR gates, Flip-Flops, inverters and RAM) which, when connected together, form more complex functions. Furthermore, each configurable element can be connected together to provide even more complex functions. A specific function to be carried out by the configurable element is determined directly by the control signals and the data stream applied to the FPGA and, ultimately, to the configurable elements within the FPGA. In a common operation, the control signals are generated, and the data stream is stored and transmitted by control logic to the FPGA. An example of external control logic for generating the control signals is a microprocessor after storing the data stream in an erasable programmable read only memory (EPROM) chip.
In order to determine the functioning of the FPGA internal cell array, it is necessary to check the AC parameters of the array. These include the interconnect delays, the propagation delay timing, the set up and hold times, and the clock widths. In order to test the AC parameters of each of the internal cells in the array, separate connections to the cells are normally used to provide inputs to the cells and determine the outputs from the individual cells. However, such an arrangement requires a large number of test pins to provide inputs and receive outputs from the large number of individual cells in the array. This discourages the checking of the AC parameters of each of the internal cells of the array.
SUMMARY OF THE INVENTION
There is a need for an AC parameter characterization arrangement for a field programmable gate array with a reduced number of inputs and outputs, but allows each of the internal cells in the array to have its operating parameters tested.
This and other needs are met by embodiments in the present invention which provide a test logic configuration for testing operating parameters of a field programmable gate array (FPGA). The FPGA has N×N configurable logic blocks. A first configurable logic block of the N×N array is configured as a pattern generator. The same or a second logic block of the N×N array is configured as a register. Another logic block of the N×N array is configured as a block under test and is coupled to the pattern generator and the register for testing of the operating parameters of the FPGA.
The earlier stated needs are also met by another embodiment of the present invention which provides an alternating current (AC) parameter characterization arrangement for a programmable gate array having an N×N internal cell array. The arrangement comprises N×N/M testing units in a programmable gate array. The testing units are serially coupled to form a chain of testing units with a single test output. Each testing unit comprises M internal cells. These internal cells include a first internal cell configured as a pattern generator that generates stimulation input, and the same or a second internal cell coupled to the pattern generator and configured as a verify register that stores output data. In preferred embodiments of the invention, all testing units include one internal cell configured as a unit under test coupled between the pattern generator and the verify register. The output of the pattern generator is received at the input of the unit under test, and the output of the unit under test is coupled to the first input of the multiplexed input arrangement.
Some of the advantages provided by the present invention are the reduced number of pins required to test each of the array cells. The testing of all of the AC parameters may be provided by controlling two clock pins, one set/reset pin, and one mode select pin and observing the output from a single primary output. Another advantage of the invention is that the cells may be reconfigured so that each of the internal cells may be tested.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part may become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention.
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Renovell et al., RAM-Based FPGA's: A Test Appraoch for the Configurable Logic, IEEE, pp. 1 to 5, Feb. 1998.*
Renovell et al., SRAM-Based FPGA's Testing the Interconnect/Logic Interface, IEEE, pp. 266 to 271, 1998.*
Renovell et al., Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA, IEEE, pp. 254 to 259, 1997.
Advanced Micro Devices , Inc.
Chase Shelly A
De'cady Albert
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