Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-02-18
2008-11-04
Dang, Phuc T (Department: 2892)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S597000, C438S639000, C257S773000, C257S776000
Reexamination Certificate
active
07446047
ABSTRACT:
A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling the spaces between the conductive lines. The polymer liner is preferably deposited on the sidewalls of the conductive lines by electro-grafting. The polymer liner may also be used in a damascene process according to a second embodiment.
REFERENCES:
patent: 5670828 (1997-09-01), Cheung et al.
patent: 5759906 (1998-06-01), Lou
patent: 5814558 (1998-09-01), Jeng et al.
patent: 5858869 (1999-01-01), Chen et al.
patent: 5948700 (1999-09-01), Zheng et al.
patent: 6130154 (2000-10-01), Yokoyama et al.
patent: 6162583 (2000-12-01), Yang et al.
patent: 6169039 (2001-01-01), Lin et al.
patent: 6214423 (2001-04-01), Lee et al.
patent: 6444564 (2002-09-01), Raeder
patent: 6445072 (2002-09-01), Subramanian et al.
patent: 2005/0079703 (2005-04-01), Chen et al.
patent: 2005/0156317 (2005-07-01), Yau et al.
Balci, N., et al., “Electrically Conductive Polymer Grafts Prepared By Electrochemical Polymerization of Pyrrole onto Poly[(methyl methacrylate)-co-(2-(N-pyrrolyl) Ethyl Methacrylate)] Electrodes,” Tr. J. of Chemistry, 22, 1998, pp. 73-80.
Ozanam, F., et al., “Kinetics Of Electrochemical Grafting Of Silicon With Organic Species,” http://www.lure.u-psud.fr/VAS10/abstracts/O-08.pdf.
Frank, C.W., et al., “Center on Polymer Interfaces and Macromolecular Assemblies,” Final Report to the National Science Foundation Materials Reseach Science and Engineering Center Program, Jun. 26, 2003, pp. 1, 8, 11-14, 49-54.
“Passivation materials for polymer electronics,” Fraunhofer ISC Annual Report, 2002, pp. 46-47.
Rappich, Dr. J., “Thin organic layers on silicon,” http://www.hmi.de/bereiche/Se/vip/organics/projects/passivation—en.html, Aug. 10, 2003, pp. 1-2.
Kalem, S., “Possible low-k solution and other potential applications,” www.eurosemi.eu.com/front-end/printer-friendly.php?newsid=5492, Jul. 1, 2004, pp. 1-7.
Lu Yung-Cheng
Tsai Minghsing
Dang Phuc T
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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