Metal stack for local interconnect layer

Details Metal stack for local interconnect layer Metal stack for local interconnect layer

2002-11-04

2004-08-10

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S685000, C438S627000

Reexamination Certificate

active

06774033

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
Interconnect layers are employed to electrically couple various nodes of an integrated circuit. An integrated circuit may have several levels of interconnect layers, with a dielectric layer providing electrical isolation between levels. A hole through a dielectric layer, referred to as a “via”, may be employed to provide electrical connectivity between two levels of interconnect layers.
An interconnect layer that is employed throughout a given level is referred to as a “regular interconnect layer”. A regular interconnect layer may be a “first metal layer”, a “second metal layer”, a “third metal layer” and so on depending on how high the regular interconnect layer is from the substrate. For example, a first regular interconnect layer above a substrate is referred to as a first metal layer, while a next regular interconnect layer above the first metal layer is referred to as a second metal layer.
An interconnect layer may also be employed in a relatively small section of an integrated circuit. Such an interconnect layer, referred to as a “local interconnect layer”, is typically formed under a first metal layer. In memory applications, for example, a local interconnect layer may provide relatively short electrical paths between devices within a cell. As is well known, the requirements for a local interconnect layer are different form that of a regular interconnect layer. That is, techniques for improving the performance of regular interconnect layers may or may not be suitable for local interconnect layers. For example, because of its function and location in the integrated circuit, a local interconnect layer has to be relatively thin compared to a regular interconnect layer to minimize the aspect ratio of resulting interconnect lines. Whereas a regular interconnect layer may be made thicker to reduce its resistivity, increasing the thickness of a local interconnect layer may not be feasible. On the other hand, because a local interconnect layer does not have to carry relatively large amounts of electrical current, its resistivity does not need to be very low.
SUMMARY
The present invention relates to an improved technique for forming a local interconnect layer in an integrated circuit. In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.


REFERENCES:
patent: 6228761 (2001-05-01), Ngo et al.
patent: 6232209 (2001-05-01), Fujiwara et al.

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